summaryrefslogtreecommitdiffstats
path: root/llvm/unittests/CodeGen/MachineOperandTest.cpp
diff options
context:
space:
mode:
authorFrancis Visoiu Mistrih <francisvm@yahoo.com>2017-12-14 10:03:14 +0000
committerFrancis Visoiu Mistrih <francisvm@yahoo.com>2017-12-14 10:03:14 +0000
commitbdaf8bfa99830bad36c9833ca6a661294fb27577 (patch)
tree578d5e8ffac8947f5141e51b8ca5cff12d89fc62 /llvm/unittests/CodeGen/MachineOperandTest.cpp
parent5df3bbf3e637b8f9175e0f96e02aab0776f1d2f1 (diff)
downloadbcm5719-llvm-bdaf8bfa99830bad36c9833ca6a661294fb27577.tar.gz
bcm5719-llvm-bdaf8bfa99830bad36c9833ca6a661294fb27577.zip
[CodeGen] Print live-out register lists as liveout(...) in both MIR and debug output
Work towards the unification of MIR and debug output by printing `liveout(...)` instead of `<regliveout>`. Only debug syntax is affected. llvm-svn: 320683
Diffstat (limited to 'llvm/unittests/CodeGen/MachineOperandTest.cpp')
-rw-r--r--llvm/unittests/CodeGen/MachineOperandTest.cpp17
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp
index 96498e681ed..5c13ddc4b8c 100644
--- a/llvm/unittests/CodeGen/MachineOperandTest.cpp
+++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp
@@ -272,4 +272,21 @@ TEST(MachineOperandTest, PrintGlobalAddress) {
}
}
+TEST(MachineOperandTest, PrintRegisterLiveOut) {
+ // Create a MachineOperand with a register live out list and print it.
+ uint32_t Mask = 0;
+ MachineOperand MO = MachineOperand::CreateRegLiveOut(&Mask);
+
+ // Checking some preconditions on the newly created
+ // MachineOperand.
+ ASSERT_TRUE(MO.isRegLiveOut());
+ ASSERT_TRUE(MO.getRegLiveOut() == &Mask);
+
+ std::string str;
+ // Print a MachineOperand containing a register live out list without a TRI.
+ raw_string_ostream OS(str);
+ MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
+ ASSERT_TRUE(OS.str() == "liveout(<unknown>)");
+}
+
} // end namespace
OpenPOWER on IntegriCloud