[CodeGen] Print RegClasses on MI in verbose mode

r322086 removed the trailing information describing reg classes for each
register.

This patch adds printing reg classes next to every register when
individual operands/instructions/basic blocks are printed. In the case
of dumping MIR or printing a full function, by default don't print it.

Differential Revision: https://reviews.llvm.org/D42239

llvm-svn: 322867

1 files changed, 3 insertions, 3 deletions

diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp
index 6861dbfe383..8f35406f160 100644
--- a/llvm/unittests/CodeGen/MachineOperandTest.cpp
+++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp
@@ -118,7 +118,6 @@ TEST(MachineOperandTest, PrintSubRegIndex) {
   // TRI and IntrinsicInfo we can print the operand as a subreg index.
   std::string str;
   raw_string_ostream OS(str);
-  ModuleSlotTracker DummyMST(nullptr);
   MachineOperand::printSubRegIdx(OS, MO.getImm(), nullptr);
   ASSERT_TRUE(OS.str() == "%subreg.3");
 }
@@ -296,7 +295,7 @@ TEST(MachineOperandTest, PrintMetadata) {
   LLVMContext Ctx;
   Module M("MachineOperandMDNodeTest", Ctx);
   NamedMDNode *MD = M.getOrInsertNamedMetadata("namedmd");
-  ModuleSlotTracker DummyMST(&M);
+  ModuleSlotTracker MST(&M);
   Metadata *MDS = MDString::get(Ctx, "foo");
   MDNode *Node = MDNode::get(Ctx, MDS);
   MD->addOperand(Node);
@@ -312,7 +311,8 @@ TEST(MachineOperandTest, PrintMetadata) {
   std::string str;
   // Print a MachineOperand containing a metadata node.
   raw_string_ostream OS(str);
-  MO.print(OS, DummyMST, LLT{}, false, false, 0, /*TRI=*/nullptr,
+  MO.print(OS, MST, LLT{}, /*PrintDef=*/false, /*IsVerbose=*/false,
+           /*ShouldPrintRegisterTies=*/false, 0, /*TRI=*/nullptr,
            /*IntrinsicInfo=*/nullptr);
   ASSERT_TRUE(OS.str() == "!0");
 }