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| author | Matt Davis <Matthew.Davis@sony.com> | 2018-05-25 18:31:28 +0000 |
|---|---|---|
| committer | Matt Davis <Matthew.Davis@sony.com> | 2018-05-25 18:31:28 +0000 |
| commit | 2d1d859c50a5cd7caf2b95d4546cdfbf95762387 (patch) | |
| tree | 8209c73f26bf0179573c6a68a485501e3dca61a3 /llvm/tools | |
| parent | 540d7e528d0aae24bcf1e717cecbe9a0aa574984 (diff) | |
| download | bcm5719-llvm-2d1d859c50a5cd7caf2b95d4546cdfbf95762387.tar.gz bcm5719-llvm-2d1d859c50a5cd7caf2b95d4546cdfbf95762387.zip | |
[llvm-mca] Update DispatchStage header comment. NFC.
Updated the comment to be a wee bit more descriptive.
llvm-svn: 333296
Diffstat (limited to 'llvm/tools')
| -rw-r--r-- | llvm/tools/llvm-mca/DispatchStage.cpp | 6 | ||||
| -rw-r--r-- | llvm/tools/llvm-mca/DispatchStage.h | 7 |
2 files changed, 10 insertions, 3 deletions
diff --git a/llvm/tools/llvm-mca/DispatchStage.cpp b/llvm/tools/llvm-mca/DispatchStage.cpp index baffb169073..3e292575d8e 100644 --- a/llvm/tools/llvm-mca/DispatchStage.cpp +++ b/llvm/tools/llvm-mca/DispatchStage.cpp @@ -8,7 +8,11 @@ //===----------------------------------------------------------------------===// /// \file /// -/// This file implements methods declared by the DispatchStage class. +/// This file models the dispatch component of an instruction pipeline. +/// +/// The DispatchStage is responsible for updating instruction dependencies +/// and communicating to the simulated instruction scheduler that an instruction +/// is ready to be scheduled for execution. /// //===----------------------------------------------------------------------===// diff --git a/llvm/tools/llvm-mca/DispatchStage.h b/llvm/tools/llvm-mca/DispatchStage.h index c2fbc53051c..574d28f8044 100644 --- a/llvm/tools/llvm-mca/DispatchStage.h +++ b/llvm/tools/llvm-mca/DispatchStage.h @@ -8,8 +8,11 @@ //===----------------------------------------------------------------------===// /// \file /// -/// This file implements classes that are used to model reorder buffers and -/// the hardware dispatch logic. +/// This file models the dispatch component of an instruction pipeline. +/// +/// The DispatchStage is responsible for updating instruction dependencies +/// and communicating to the simulated instruction scheduler that an instruction +/// is ready to be scheduled for execution. /// //===----------------------------------------------------------------------===// |

