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authorReid Spencer <rspencer@reidspencer.com>2006-11-02 01:53:59 +0000
committerReid Spencer <rspencer@reidspencer.com>2006-11-02 01:53:59 +0000
commit7eb55b395fdbbdbd113aabb6cad51cc98b379af0 (patch)
tree2666f67e03e73fc890b7277073186b32ead86d50 /llvm/tools/llvm2cpp/CppWriter.cpp
parent57382066e875c05e58f35db5976a22ed5dcdebf8 (diff)
downloadbcm5719-llvm-7eb55b395fdbbdbd113aabb6cad51cc98b379af0.tar.gz
bcm5719-llvm-7eb55b395fdbbdbd113aabb6cad51cc98b379af0.zip
For PR950:
Replace the REM instruction with UREM, SREM and FREM. llvm-svn: 31369
Diffstat (limited to 'llvm/tools/llvm2cpp/CppWriter.cpp')
-rw-r--r--llvm/tools/llvm2cpp/CppWriter.cpp12
1 files changed, 9 insertions, 3 deletions
diff --git a/llvm/tools/llvm2cpp/CppWriter.cpp b/llvm/tools/llvm2cpp/CppWriter.cpp
index 089f1cac219..f74294fb3f2 100644
--- a/llvm/tools/llvm2cpp/CppWriter.cpp
+++ b/llvm/tools/llvm2cpp/CppWriter.cpp
@@ -776,7 +776,9 @@ void CppWriter::printConstant(const Constant *CV) {
case Instruction::UDiv: Out << "getUDiv"; break;
case Instruction::SDiv: Out << "getSDiv"; break;
case Instruction::FDiv: Out << "getFDiv"; break;
- case Instruction::Rem: Out << "getRem"; break;
+ case Instruction::URem: Out << "getURem"; break;
+ case Instruction::SRem: Out << "getSRem"; break;
+ case Instruction::FRem: Out << "getFRem"; break;
case Instruction::And: Out << "getAnd"; break;
case Instruction::Or: Out << "getOr"; break;
case Instruction::Xor: Out << "getXor"; break;
@@ -1026,7 +1028,9 @@ CppWriter::printInstruction(const Instruction *I, const std::string& bbname) {
case Instruction::UDiv:
case Instruction::SDiv:
case Instruction::FDiv:
- case Instruction::Rem:
+ case Instruction::URem:
+ case Instruction::SRem:
+ case Instruction::FRem:
case Instruction::And:
case Instruction::Or:
case Instruction::Xor:
@@ -1040,7 +1044,9 @@ CppWriter::printInstruction(const Instruction *I, const std::string& bbname) {
case Instruction::UDiv:Out << "Instruction::UDiv"; break;
case Instruction::SDiv:Out << "Instruction::SDiv"; break;
case Instruction::FDiv:Out << "Instruction::FDiv"; break;
- case Instruction::Rem: Out << "Instruction::Rem"; break;
+ case Instruction::URem:Out << "Instruction::URem"; break;
+ case Instruction::SRem:Out << "Instruction::SRem"; break;
+ case Instruction::FRem:Out << "Instruction::FRem"; break;
case Instruction::And: Out << "Instruction::And"; break;
case Instruction::Or: Out << "Instruction::Or"; break;
case Instruction::Xor: Out << "Instruction::Xor"; break;
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