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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-03-18 15:33:27 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-03-18 15:33:27 +0000 |
| commit | e64f3b108d4896275ad89f5000bb389ad8eef758 (patch) | |
| tree | 525b46233eb5d13966dc7fe8f40465585df9dcde /llvm/tools/llvm-shlib/libllvm.cpp | |
| parent | 63b1028953cf688c687fc5f3168ab948a50fcc54 (diff) | |
| download | bcm5719-llvm-e64f3b108d4896275ad89f5000bb389ad8eef758.tar.gz bcm5719-llvm-e64f3b108d4896275ad89f5000bb389ad8eef758.zip | |
[llvm-mca] Allow the definition of multiple register files.
This is a refactoring in preparation for other two changes that will allow
scheduling models to define multiple register files. This is the first step
towards fixing PR36662.
class RegisterFile (in Dispatch.h) now can emulate multiple register files.
Internally, it tracks the number of available physical registers in each
register file (described by class RegisterFileInfo).
Each register file is associated to a list of MCRegisterClass indices. Knowing
the register class indices allows to map physical registers to register files.
The long term goal is to allow processor models to optionally specify how many
register files are implemented via tablegen.
Differential Revision: https://reviews.llvm.org/D44488
llvm-svn: 327798
Diffstat (limited to 'llvm/tools/llvm-shlib/libllvm.cpp')
0 files changed, 0 insertions, 0 deletions

