summaryrefslogtreecommitdiffstats
path: root/llvm/tools/llvm-rc/ResourceScriptParser.cpp
diff options
context:
space:
mode:
authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2018-11-29 12:15:56 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2018-11-29 12:15:56 +0000
commit373a4ccf6cdd69993fbcef7384b741373374269b (patch)
tree43b0aeb707a77caada49a5fc6c181670691d9c16 /llvm/tools/llvm-rc/ResourceScriptParser.cpp
parent10c63835ad33c1d1a9b0d1609948882bc80eacc3 (diff)
downloadbcm5719-llvm-373a4ccf6cdd69993fbcef7384b741373374269b.tar.gz
bcm5719-llvm-373a4ccf6cdd69993fbcef7384b741373374269b.zip
[llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).
This patch adds the ability to specify via tablegen which processor resources are load/store queue resources. A new tablegen class named MemoryQueue can be optionally used to mark resources that model load/store queues. Information about the load/store queue is collected at 'CodeGenSchedule' stage, and analyzed by the 'SubtargetEmitter' to initialize two new fields in struct MCExtraProcessorInfo named `LoadQueueID` and `StoreQueueID`. Those two fields are identifiers for buffered resources used to describe the load queue and the store queue. Field `BufferSize` is interpreted as the number of entries in the queue, while the number of units is a throughput indicator (i.e. number of available pickers for loads/stores). At construction time, LSUnit in llvm-mca checks for the presence of extra processor information (i.e. MCExtraProcessorInfo) in the scheduling model. If that information is available, and fields LoadQueueID and StoreQueueID are set to a value different than zero (i.e. the invalid processor resource index), then LSUnit initializes its LoadQueue/StoreQueue based on the BufferSize value declared by the two processor resources. With this patch, we more accurately track dynamic dispatch stalls caused by the lack of LS tokens (i.e. load/store queue full). This is also shown by the differences in two BdVer2 tests. Stalls that were previously classified as generic SCHEDULER FULL stalls, are not correctly classified either as "load queue full" or "store queue full". About the differences in the -scheduler-stats view: those differences are expected, because entries in the load/store queue are not released at instruction issue stage. Instead, those are released at instruction executed stage. This is the main reason why for the modified tests, the load/store queues gets full before PdEx is full. Differential Revision: https://reviews.llvm.org/D54957 llvm-svn: 347857
Diffstat (limited to 'llvm/tools/llvm-rc/ResourceScriptParser.cpp')
0 files changed, 0 insertions, 0 deletions
OpenPOWER on IntegriCloud