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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-04-11 14:02:41 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-04-11 14:02:41 +0000 |
| commit | f26b723491ee2d998f2a44001005318f6c171243 (patch) | |
| tree | f0fdf72925d15ab534572f9beaa878baed6aa854 /llvm/tools/llvm-mca/View.cpp | |
| parent | 5782ec29abd5719f6cdd666c86a9e4c6ea0727a8 (diff) | |
| download | bcm5719-llvm-f26b723491ee2d998f2a44001005318f6c171243.tar.gz bcm5719-llvm-f26b723491ee2d998f2a44001005318f6c171243.zip | |
[AMDGPU] Ensure there are enough registers for wave dispatch
Summary:
This fixes the number of SGPRs and VGPRs in the *_RSRC1 register to
allow for registers set up in wave dispatch, even if those registers are
not used in the shader.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45503
Change-Id: I6575f0e0d2a528d1319d0b289f0ebe4510fa5771
llvm-svn: 329808
Diffstat (limited to 'llvm/tools/llvm-mca/View.cpp')
0 files changed, 0 insertions, 0 deletions
