[llvm-mca] Add the RetireStage.

Summary:
This class maintains the same logic as the original RetireControlUnit.

This is just an intermediate patch to make the RCU a Stage.  Future patches will remove the dependency on the DispatchStage, and then more properly populate the pre/execute/post Stage interface.  

Reviewers: andreadb, RKSimon, courbet

Reviewed By: andreadb, courbet

Subscribers: javed.absar, mgorny, tschuett, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D47244

llvm-svn: 333292

1 files changed, 5 insertions, 9 deletions

diff --git a/llvm/tools/llvm-mca/Scheduler.h b/llvm/tools/llvm-mca/Scheduler.h
index 337737a5318..f8dce3c2e9b 100644
--- a/llvm/tools/llvm-mca/Scheduler.h
+++ b/llvm/tools/llvm-mca/Scheduler.h
@@ -17,6 +17,7 @@
 
 #include "Instruction.h"
 #include "LSUnit.h"
+#include "RetireControlUnit.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
@@ -24,7 +25,6 @@
 namespace mca {
 
 class Backend;
-class DispatchStage;
 
 /// Used to notify the internal state of a processor resource.
 ///
@@ -402,6 +402,7 @@ public:
 /// An Instruction leaves the IssuedQueue when it reaches the write-back stage.
 class Scheduler {
   const llvm::MCSchedModel &SM;
+  RetireControlUnit &RCU;
 
   // Hardware resources that are managed by this scheduler.
   std::unique_ptr<ResourceManager> Resources;
@@ -410,9 +411,6 @@ class Scheduler {
   // The Backend gets notified when instructions are ready/issued/executed.
   Backend *const Owner;
 
-  // The dispatch unit gets notified when instructions are executed.
-  DispatchStage *DS;
-
   using QueueEntryTy = std::pair<unsigned, Instruction *>;
   std::map<unsigned, Instruction *> WaitQueue;
   std::map<unsigned, Instruction *> ReadyQueue;
@@ -447,15 +445,13 @@ class Scheduler {
   void updateIssuedQueue(llvm::SmallVectorImpl<InstRef> &Executed);
 
 public:
-  Scheduler(Backend *B, const llvm::MCSchedModel &Model, unsigned LoadQueueSize,
-            unsigned StoreQueueSize, bool AssumeNoAlias)
-      : SM(Model), Resources(llvm::make_unique<ResourceManager>(SM)),
+  Scheduler(Backend *B, const llvm::MCSchedModel &Model, RetireControlUnit &R,
+            unsigned LoadQueueSize, unsigned StoreQueueSize, bool AssumeNoAlias)
+      : SM(Model), RCU(R), Resources(llvm::make_unique<ResourceManager>(SM)),
         LSU(llvm::make_unique<LSUnit>(LoadQueueSize, StoreQueueSize,
                                       AssumeNoAlias)),
         Owner(B) {}
 
-  void setDispatchStage(DispatchStage *DispStage) { DS = DispStage; }
-
   /// Check if the instruction in 'IR' can be dispatched.
   ///
   /// The DispatchStage is responsible for querying the Scheduler before