[llvm-mca] Avoid exposing index values in the MCA interfaces.

Summary:
This patch eliminates many places where we originally needed to  pass index
values to represent an instruction.  The index is still used as a key, in various parts of 
MCA.  I'm  not comfortable eliminating the index just yet.    By burying the index in
the instruction, we can avoid exposing that value in many places.

Eventually, we should consider removing the Instructions list in the Backend 
all together,   it's only used to hold and reclaim the memory for the allocated 
Instruction instances.  Instead we could pass around a smart pointer.  But that's
a separate discussion/patch.

Reviewers: andreadb, courbet, RKSimon

Reviewed By: andreadb

Subscribers: javed.absar, tschuett, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D46367

llvm-svn: 331660

1 files changed, 12 insertions, 12 deletions

diff --git a/llvm/tools/llvm-mca/Scheduler.h b/llvm/tools/llvm-mca/Scheduler.h
index 25bc87e3eba..b4bd5ef930b 100644
--- a/llvm/tools/llvm-mca/Scheduler.h
+++ b/llvm/tools/llvm-mca/Scheduler.h
@@ -419,10 +419,10 @@ class Scheduler {
   std::map<unsigned, Instruction *> IssuedQueue;
 
   void
-  notifyInstructionIssued(unsigned Index,
+  notifyInstructionIssued(const InstRef &IR,
                           llvm::ArrayRef<std::pair<ResourceRef, double>> Used);
-  void notifyInstructionExecuted(unsigned Index);
-  void notifyInstructionReady(unsigned Index);
+  void notifyInstructionExecuted(const InstRef &IR);
+  void notifyInstructionReady(const InstRef &IR);
   void notifyResourceAvailable(const ResourceRef &RR);
 
   // Notify the Backend that buffered resources were consumed.
@@ -432,19 +432,19 @@ class Scheduler {
 
   /// Select the next instruction to issue from the ReadyQueue.
   /// This method gives priority to older instructions.
-  std::pair<unsigned, Instruction *> select();
+  InstRef select();
 
   /// Move instructions from the WaitQueue to the ReadyQueue if input operands
   /// are all available.
-  void promoteToReadyQueue(llvm::SmallVectorImpl<unsigned> &Ready);
+  void promoteToReadyQueue(llvm::SmallVectorImpl<InstRef> &Ready);
 
   /// Issue an instruction without updating the ready queue.
   void issueInstructionImpl(
-      unsigned Index, Instruction &IS,
+      InstRef &IR,
       llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Pipes);
 
-  void updatePendingQueue(llvm::SmallVectorImpl<unsigned> &Ready);
-  void updateIssuedQueue(llvm::SmallVectorImpl<unsigned> &Executed);
+  void updatePendingQueue(llvm::SmallVectorImpl<InstRef> &Ready);
+  void updateIssuedQueue(llvm::SmallVectorImpl<InstRef> &Executed);
 
 public:
   Scheduler(Backend *B, const llvm::MCSchedModel &Model, unsigned LoadQueueSize,
@@ -456,18 +456,18 @@ public:
 
   void setDispatchUnit(DispatchUnit *DispUnit) { DU = DispUnit; }
 
-  /// Check if instruction at index Idx can be dispatched.
+  /// Check if the instruction in 'IR' can be dispatched.
   ///
   /// The DispatchUnit is responsible for querying the Scheduler before
   /// dispatching new instructions. Queries are performed through method
   /// `Scheduler::CanBeDispatched`. If scheduling resources are available,
   /// and the instruction can be dispatched, then this method returns true.
   /// Otherwise, a generic HWStallEvent is notified to the listeners.
-  bool canBeDispatched(unsigned Idx, const InstrDesc &Desc) const;
-  void scheduleInstruction(unsigned Idx, Instruction &MCIS);
+  bool canBeDispatched(const InstRef &IR) const;
+  void scheduleInstruction(InstRef &IR);
 
   /// Issue an instruction.
-  void issueInstruction(unsigned Index, Instruction &IS);
+  void issueInstruction(InstRef &IR);
 
   /// Reserve one entry in each buffered resource.
   void reserveBuffers(llvm::ArrayRef<uint64_t> Buffers) {