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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-08-21 12:40:15 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-08-21 12:40:15 +0000 |
commit | 5184995f9b7ff867dd458b638ccb1c5bc77239c1 (patch) | |
tree | 375dd1e017c0779f88e544805bbf3a3b772faf02 /llvm/tools/llvm-mca/RegisterFile.cpp | |
parent | b59b45e7f1bd7486d8d30bd5c08f08c4b71dcca9 (diff) | |
download | bcm5719-llvm-5184995f9b7ff867dd458b638ccb1c5bc77239c1.tar.gz bcm5719-llvm-5184995f9b7ff867dd458b638ccb1c5bc77239c1.zip |
[llvm-mca] Add method cycleEvent() to class Scheduler. NFCI
The goal of this patch is to simplify the Scheduler's interface in preparation
for D50929.
Some methods in the Scheduler's interface should not be exposed to external
users, since their presence makes it hard to both understand, and extend the
Scheduler's interface.
This patch removes the following two methods from the public Scheduler's API:
- reclaimSimulatedResources()
- updatePendingQueue()
Their logic has been migrated to a new method named 'cycleEvent()'.
Methods 'updateIssuedSet()' and 'promoteToReadySet()' still exist. However,
they are now private members of class Scheduler.
This simplifies the interaction with the Scheduler from the ExecuteStage.
llvm-svn: 340273
Diffstat (limited to 'llvm/tools/llvm-mca/RegisterFile.cpp')
-rw-r--r-- | llvm/tools/llvm-mca/RegisterFile.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/tools/llvm-mca/RegisterFile.cpp b/llvm/tools/llvm-mca/RegisterFile.cpp index ea27a8b9b68..cba17a6a6a1 100644 --- a/llvm/tools/llvm-mca/RegisterFile.cpp +++ b/llvm/tools/llvm-mca/RegisterFile.cpp @@ -166,7 +166,7 @@ void RegisterFile::addRegisterWrite(WriteRef Write, const RegisterRenamingInfo &RRI = RegisterMappings[RegID].second; if (RRI.RenameAs && RRI.RenameAs != RegID) { RegID = RRI.RenameAs; - const WriteRef &OtherWrite = RegisterMappings[RegID].first; + WriteRef &OtherWrite = RegisterMappings[RegID].first; if (!WS.clearsSuperRegisters()) { // The processor keeps the definition of `RegID` together with register @@ -174,7 +174,8 @@ void RegisterFile::addRegisterWrite(WriteRef Write, // register is allocated. ShouldAllocatePhysRegs = false; - if (OtherWrite.getSourceIndex() != Write.getSourceIndex()) { + if (OtherWrite.getWriteState() && + (OtherWrite.getSourceIndex() != Write.getSourceIndex())) { // This partial write has a false dependency on RenameAs. WS.setDependentWrite(OtherWrite.getWriteState()); } |