[MC][Tablegen] Allow models to describe the retire control unit for llvm-mca.

This patch adds the ability to describe properties of the hardware retire
control unit.

Tablegen class RetireControlUnit has been added for this purpose (see
TargetSchedule.td).

A RetireControlUnit specifies the size of the reorder buffer, as well as the
maximum number of opcodes that can be retired every cycle.

A zero (or negative) value for the reorder buffer size means: "the size is
unknown". If the size is unknown, then llvm-mca defaults it to the value of
field SchedMachineModel::MicroOpBufferSize.  A zero or negative number of
opcodes retired per cycle means: "there is no restriction on the number of
instructions that can be retired every cycle".

Models can optionally specify an instance of RetireControlUnit. There can only
be up-to one RetireControlUnit definition per scheduling model.

Information related to the RCU (RetireControlUnit) is stored in (two new fields
of) MCExtraProcessorInfo.  llvm-mca loads that information when it initializes
the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp).

This patch fixes PR36661.

Differential Revision: https://reviews.llvm.org/D45259

llvm-svn: 329304

1 files changed, 6 insertions, 14 deletions

diff --git a/llvm/tools/llvm-mca/Dispatch.h b/llvm/tools/llvm-mca/Dispatch.h
index 979e2a370dd..3f09ab78611 100644
--- a/llvm/tools/llvm-mca/Dispatch.h
+++ b/llvm/tools/llvm-mca/Dispatch.h
@@ -192,12 +192,7 @@ private:
   DispatchUnit *Owner;
 
 public:
-  RetireControlUnit(unsigned NumSlots, DispatchUnit *DU)
-      : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
-        AvailableSlots(NumSlots), MaxRetirePerCycle(0), Owner(DU) {
-    assert(NumSlots && "Expected at least one slot!");
-    Queue.resize(NumSlots);
-  }
+  RetireControlUnit(const llvm::MCSchedModel &SM, DispatchUnit *DU);
 
   bool isFull() const { return !AvailableSlots; }
   bool isEmpty() const { return AvailableSlots == Queue.size(); }
@@ -264,16 +259,13 @@ class DispatchUnit {
                                    llvm::ArrayRef<unsigned> UsedPhysRegs);
 
 public:
-  DispatchUnit(Backend *B, const llvm::MCSubtargetInfo &STI,
-               const llvm::MCRegisterInfo &MRI, unsigned MicroOpBufferSize,
-               unsigned RegisterFileSize, unsigned MaxDispatchWidth,
-               Scheduler *Sched)
+  DispatchUnit(Backend *B, const llvm::MCSchedModel &SM,
+               const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
+               unsigned MaxDispatchWidth, Scheduler *Sched)
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
         CarryOver(0U), SC(Sched),
-        RAT(llvm::make_unique<RegisterFile>(STI.getSchedModel(), MRI,
-                                            RegisterFileSize)),
-        RCU(llvm::make_unique<RetireControlUnit>(MicroOpBufferSize, this)),
-        Owner(B) {}
+        RAT(llvm::make_unique<RegisterFile>(SM, MRI, RegisterFileSize)),
+        RCU(llvm::make_unique<RetireControlUnit>(SM, this)), Owner(B) {}
 
   unsigned getDispatchWidth() const { return DispatchWidth; }