[llvm-exegesis][NFC] moving code around.

Summary: Renaming InstructionBuilder into InstructionTemplate and moving code generation tools from MCInstrDescView to CodeTemplate.

Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D52592

llvm-svn: 343188

1 files changed, 18 insertions, 17 deletions

diff --git a/llvm/tools/llvm-exegesis/lib/Uops.cpp b/llvm/tools/llvm-exegesis/lib/Uops.cpp
index d7ac880d051..21dae3c2604 100644
--- a/llvm/tools/llvm-exegesis/lib/Uops.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Uops.cpp
@@ -127,23 +127,23 @@ UopsSnippetGenerator::~UopsSnippetGenerator() = default;
 
 void UopsSnippetGenerator::instantiateMemoryOperands(
     const unsigned ScratchSpacePointerInReg,
-    std::vector<InstructionBuilder> &Instructions) const {
+    std::vector<InstructionTemplate> &Instructions) const {
   if (ScratchSpacePointerInReg == 0)
     return; // no memory operands.
   const auto &ET = State.getExegesisTarget();
   const unsigned MemStep = ET.getMaxMemoryAccessSize();
   const size_t OriginalInstructionsSize = Instructions.size();
   size_t I = 0;
-  for (InstructionBuilder &IB : Instructions) {
-    ET.fillMemoryOperands(IB, ScratchSpacePointerInReg, I * MemStep);
+  for (InstructionTemplate &IT : Instructions) {
+    ET.fillMemoryOperands(IT, ScratchSpacePointerInReg, I * MemStep);
     ++I;
   }
 
   while (Instructions.size() < kMinNumDifferentAddresses) {
-    InstructionBuilder IB = Instructions[I % OriginalInstructionsSize];
-    ET.fillMemoryOperands(IB, ScratchSpacePointerInReg, I * MemStep);
+    InstructionTemplate IT = Instructions[I % OriginalInstructionsSize];
+    ET.fillMemoryOperands(IT, ScratchSpacePointerInReg, I * MemStep);
     ++I;
-    Instructions.push_back(std::move(IB));
+    Instructions.push_back(std::move(IT));
   }
   assert(I * MemStep < BenchmarkRunner::ScratchSpace::kSize &&
          "not enough scratch space");
@@ -178,16 +178,16 @@ UopsSnippetGenerator::generateCodeTemplate(unsigned Opcode) const {
   }
 
   const AliasingConfigurations SelfAliasing(Instr, Instr);
-  InstructionBuilder IB(Instr);
+  InstructionTemplate IT(Instr);
   if (SelfAliasing.empty()) {
     CT.Info = "instruction is parallel, repeating a random one.";
-    CT.Instructions.push_back(std::move(IB));
+    CT.Instructions.push_back(std::move(IT));
     instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
     return std::move(CT);
   }
   if (SelfAliasing.hasImplicitAliasing()) {
     CT.Info = "instruction is serial, repeating a random one.";
-    CT.Instructions.push_back(std::move(IB));
+    CT.Instructions.push_back(std::move(IT));
     instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
     return std::move(CT);
   }
@@ -206,9 +206,9 @@ UopsSnippetGenerator::generateCodeTemplate(unsigned Opcode) const {
     for (const llvm::MCPhysReg Reg : Op.Tracker->sourceBits().set_bits()) {
       if (ScratchSpaceAliasedRegs && ScratchSpaceAliasedRegs->test(Reg))
         continue; // Do not use the scratch memory address register.
-      InstructionBuilder TmpIB = IB;
-      TmpIB.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
-      CT.Instructions.push_back(std::move(TmpIB));
+      InstructionTemplate TmpIT = IT;
+      TmpIT.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
+      CT.Instructions.push_back(std::move(TmpIT));
     }
     instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
     return std::move(CT);
@@ -225,7 +225,7 @@ UopsSnippetGenerator::generateCodeTemplate(unsigned Opcode) const {
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
       Defs.set(RandomReg);
-      IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
+      IT.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
   // And pick random use values that are not reserved and don't alias with defs.
@@ -240,12 +240,12 @@ UopsSnippetGenerator::generateCodeTemplate(unsigned Opcode) const {
       remove(PossibleRegisters, DefAliases);
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
-      IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
+      IT.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
   CT.Info =
       "instruction has no tied variables picking Uses different from defs";
-  CT.Instructions.push_back(std::move(IB));
+  CT.Instructions.push_back(std::move(IT));
   instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
   return std::move(CT);
 }
@@ -278,7 +278,7 @@ UopsBenchmarkRunner::runMeasurements(const ExecutableFunction &Function,
   };
 
   std::vector<BenchmarkMeasure> Result;
-  const auto& PfmCounters = SchedModel.getExtraProcessorInfo().PfmCounters;
+  const auto &PfmCounters = SchedModel.getExtraProcessorInfo().PfmCounters;
   // Uops per port.
   for (unsigned ProcResIdx = 1;
        ProcResIdx < SchedModel.getNumProcResourceKinds(); ++ProcResIdx) {
@@ -286,7 +286,8 @@ UopsBenchmarkRunner::runMeasurements(const ExecutableFunction &Function,
     if (!Counters)
       continue;
     const double CounterValue = RunMeasurement(Counters);
-    Result.push_back(BenchmarkMeasure::Create(SchedModel.getProcResource(ProcResIdx)->Name, CounterValue));
+    Result.push_back(BenchmarkMeasure::Create(
+        SchedModel.getProcResource(ProcResIdx)->Name, CounterValue));
   }
   // NumMicroOps.
   if (const char *const UopsCounter = PfmCounters.UopsCounter) {