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author | Clement Courbet <courbet@google.com> | 2018-06-25 13:44:27 +0000 |
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committer | Clement Courbet <courbet@google.com> | 2018-06-25 13:44:27 +0000 |
commit | 0e8bf4e5aa7dc53bbeaf073639bcda239feab901 (patch) | |
tree | 6ad502e0294cb33ffca2863d94ea83ecdaa6e612 /llvm/tools/llvm-exegesis/lib/Uops.cpp | |
parent | 0ac29350b5c081fa0dd469ca618a5857d659f3b0 (diff) | |
download | bcm5719-llvm-0e8bf4e5aa7dc53bbeaf073639bcda239feab901.tar.gz bcm5719-llvm-0e8bf4e5aa7dc53bbeaf073639bcda239feab901.zip |
[llvm-exegesis][NFC] Remove unnecessary member variables.
llvm-svn: 335470
Diffstat (limited to 'llvm/tools/llvm-exegesis/lib/Uops.cpp')
-rw-r--r-- | llvm/tools/llvm-exegesis/lib/Uops.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/tools/llvm-exegesis/lib/Uops.cpp b/llvm/tools/llvm-exegesis/lib/Uops.cpp index 349f5f4eaa4..677a9d3a104 100644 --- a/llvm/tools/llvm-exegesis/lib/Uops.cpp +++ b/llvm/tools/llvm-exegesis/lib/Uops.cpp @@ -139,7 +139,7 @@ InstructionBenchmark::ModeE UopsBenchmarkRunner::getMode() const { llvm::Expected<SnippetPrototype> UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const { - const auto &InstrDesc = MCInstrInfo.get(Opcode); + const auto &InstrDesc = State.getInstrInfo().get(Opcode); if (auto E = isInfeasible(InstrDesc)) return std::move(E); const Instruction Instr(InstrDesc, RATC); @@ -179,7 +179,7 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const { } InstructionInstance II(Instr); // No tied variables, we pick random values for defs. - llvm::BitVector Defs(MCRegisterInfo.getNumRegs()); + llvm::BitVector Defs(State.getRegInfo().getNumRegs()); for (const auto &Op : Instr.Operands) { if (Op.Tracker && Op.IsExplicit && Op.IsDef) { auto PossibleRegisters = Op.Tracker->sourceBits(); @@ -191,7 +191,7 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const { } } // And pick random use values that are not reserved and don't alias with defs. - const auto DefAliases = getAliasedBits(MCRegisterInfo, Defs); + const auto DefAliases = getAliasedBits(State.getRegInfo(), Defs); for (const auto &Op : Instr.Operands) { if (Op.Tracker && Op.IsExplicit && !Op.IsDef) { auto PossibleRegisters = Op.Tracker->sourceBits(); |