[llvm-exegesis][X86] Handle CMOVcc/SETcc OPERAND_COND_CODE OperandType

Summary:
D60041 / D60138 refactoring changed how CMOV/SETcc opcodes
are handled. concode is now an immediate, with it's own operand type.

This at least allows to not crash on the opcode.
However, this still won't generate all the snippets
with all the condcode enumerators. D60066 does that.

Reviewers: courbet, gchatelet

Reviewed By: gchatelet

Subscribers: tschuett, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60057

llvm-svn: 357841

1 files changed, 5 insertions, 26 deletions

diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index 44592fd89a3..8cbde9f0186 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -12,6 +12,7 @@
 #include "Assembler.h"
 #include "MCInstrDescView.h"
 #include "SnippetGenerator.h"
+#include "Target.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
@@ -50,7 +51,7 @@ SnippetGenerator::generateConfigurations(const Instruction &Instr) const {
         BenchmarkCode BC;
         BC.Info = CT.Info;
         for (InstructionTemplate &IT : CT.Instructions) {
-          randomizeUnsetVariables(ForbiddenRegs, IT);
+          randomizeUnsetVariables(State.getExegesisTarget(), ForbiddenRegs, IT);
           BC.Instructions.push_back(IT.build());
         }
         if (CT.ScratchSpacePointerInReg)
@@ -156,29 +157,6 @@ static auto randomElement(const C &Container) -> decltype(Container[0]) {
   return Container[randomIndex(Container.size())];
 }
 
-static void randomize(const Instruction &Instr, const Variable &Var,
-                      llvm::MCOperand &AssignedValue,
-                      const llvm::BitVector &ForbiddenRegs) {
-  const Operand &Op = Instr.getPrimaryOperand(Var);
-  switch (Op.getExplicitOperandInfo().OperandType) {
-  case llvm::MCOI::OperandType::OPERAND_IMMEDIATE:
-    // FIXME: explore immediate values too.
-    AssignedValue = llvm::MCOperand::createImm(1);
-    break;
-  case llvm::MCOI::OperandType::OPERAND_REGISTER: {
-    assert(Op.isReg());
-    auto AllowedRegs = Op.getRegisterAliasing().sourceBits();
-    assert(AllowedRegs.size() == ForbiddenRegs.size());
-    for (auto I : ForbiddenRegs.set_bits())
-      AllowedRegs.reset(I);
-    AssignedValue = llvm::MCOperand::createReg(randomBit(AllowedRegs));
-    break;
-  }
-  default:
-    break;
-  }
-}
-
 static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
                                     InstructionTemplate &IB) {
   assert(ROV.Op);
@@ -212,12 +190,13 @@ void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
   setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
 }
 
-void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs,
+void randomizeUnsetVariables(const ExegesisTarget &Target,
+                             const llvm::BitVector &ForbiddenRegs,
                              InstructionTemplate &IT) {
   for (const Variable &Var : IT.Instr.Variables) {
     llvm::MCOperand &AssignedValue = IT.getValueFor(Var);
     if (!AssignedValue.isValid())
-      randomize(IT.Instr, Var, AssignedValue, ForbiddenRegs);
+      Target.randomizeMCOperand(IT.Instr, Var, AssignedValue, ForbiddenRegs);
   }
 }