reland r332579: [llvm-exegesis] Update to cover latency through another opcode.

Restructuring the code to measure latency and uops.
The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash).
It now uses BitVector instead of Graph for performance reasons.

https://reviews.llvm.org/D46821

(with fixed ARM tests)

Authored by Guillaume Chatelet

llvm-svn: 332592

1 files changed, 83 insertions, 0 deletions

diff --git a/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp b/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp
new file mode 100644
index 00000000000..fb5547bb603
--- /dev/null
+++ b/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp
@@ -0,0 +1,83 @@
+//===-- RegisterAliasingTracker.cpp -----------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RegisterAliasing.h"
+
+namespace exegesis {
+
+llvm::BitVector getAliasedBits(const llvm::MCRegisterInfo &RegInfo,
+                               const llvm::BitVector &SourceBits) {
+  llvm::BitVector AliasedBits(RegInfo.getNumRegs());
+  for (const size_t PhysReg : SourceBits.set_bits()) {
+    using RegAliasItr = llvm::MCRegAliasIterator;
+    for (auto Itr = RegAliasItr(PhysReg, &RegInfo, true); Itr.isValid();
+         ++Itr) {
+      AliasedBits.set(*Itr);
+    }
+  }
+  return AliasedBits;
+}
+
+RegisterAliasingTracker::RegisterAliasingTracker(
+    const llvm::MCRegisterInfo &RegInfo)
+    : SourceBits(RegInfo.getNumRegs()), AliasedBits(RegInfo.getNumRegs()),
+      Origins(RegInfo.getNumRegs()) {}
+
+RegisterAliasingTracker::RegisterAliasingTracker(
+    const llvm::MCRegisterInfo &RegInfo, const llvm::BitVector &ReservedReg,
+    const llvm::MCRegisterClass &RegClass)
+    : RegisterAliasingTracker(RegInfo) {
+  for (llvm::MCPhysReg PhysReg : RegClass)
+    if (!ReservedReg[PhysReg]) // Removing reserved registers.
+      SourceBits.set(PhysReg);
+  FillOriginAndAliasedBits(RegInfo, SourceBits);
+}
+
+RegisterAliasingTracker::RegisterAliasingTracker(
+    const llvm::MCRegisterInfo &RegInfo, const llvm::MCPhysReg PhysReg)
+    : RegisterAliasingTracker(RegInfo) {
+  SourceBits.set(PhysReg);
+  FillOriginAndAliasedBits(RegInfo, SourceBits);
+}
+
+void RegisterAliasingTracker::FillOriginAndAliasedBits(
+    const llvm::MCRegisterInfo &RegInfo, const llvm::BitVector &SourceBits) {
+  using RegAliasItr = llvm::MCRegAliasIterator;
+  for (const size_t PhysReg : SourceBits.set_bits()) {
+    for (auto Itr = RegAliasItr(PhysReg, &RegInfo, true); Itr.isValid();
+         ++Itr) {
+      AliasedBits.set(*Itr);
+      Origins[*Itr] = PhysReg;
+    }
+  }
+}
+
+RegisterAliasingTrackerCache::RegisterAliasingTrackerCache(
+    const llvm::MCRegisterInfo &RegInfo, const llvm::BitVector &ReservedReg)
+    : RegInfo(RegInfo), ReservedReg(ReservedReg),
+      EmptyRegisters(RegInfo.getNumRegs()) {}
+
+const RegisterAliasingTracker &
+RegisterAliasingTrackerCache::getRegister(llvm::MCPhysReg PhysReg) {
+  auto &Found = Registers[PhysReg];
+  if (!Found)
+    Found.reset(new RegisterAliasingTracker(RegInfo, PhysReg));
+  return *Found;
+}
+
+const RegisterAliasingTracker &
+RegisterAliasingTrackerCache::getRegisterClass(unsigned RegClassIndex) {
+  auto &Found = RegisterClasses[RegClassIndex];
+  const auto &RegClass = RegInfo.getRegClass(RegClassIndex);
+  if (!Found)
+    Found.reset(new RegisterAliasingTracker(RegInfo, ReservedReg, RegClass));
+  return *Found;
+}
+
+} // namespace exegesis