[llvm-exegeis] Computing Latency configuration upfront so we can generate many CodeTemplates at once.

Summary: LatencyGenerator now computes all possible mode of serial execution for an Instruction upfront and generates CodeTemplate for the ones that give the best results (e.g. no need to generate a two instructions snippet when repeating a single one would do). The next step is to generate even more configurations for cases (e.g. for XOR we should generate "XOR EAX, EAX, EAX" and "XOR EAX, EAX, EBX")

Reviewers: courbet

Reviewed By: courbet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D53320

llvm-svn: 344689

1 files changed, 50 insertions, 0 deletions

diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
index 34433daa231..df9d18b94bb 100644
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
@@ -65,4 +65,54 @@ llvm::MCInst InstructionTemplate::build() const {
   return Result;
 }
 
+bool isEnumValue(ExecutionMode Execution) {
+  return llvm::isPowerOf2_32(static_cast<uint32_t>(Execution));
+}
+
+llvm::StringRef getName(ExecutionMode Bit) {
+  assert(isEnumValue(Bit) && "Bit must be a power of two");
+  switch (Bit) {
+  case ExecutionMode::UNKNOWN:
+    return "UNKNOWN";
+  case ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS:
+    return "ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS";
+  case ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS:
+    return "ALWAYS_SERIAL_TIED_REGS_ALIAS";
+  case ExecutionMode::SERIAL_VIA_MEMORY_INSTR:
+    return "SERIAL_VIA_MEMORY_INSTR";
+  case ExecutionMode::SERIAL_VIA_EXPLICIT_REGS:
+    return "SERIAL_VIA_EXPLICIT_REGS";
+  case ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR:
+    return "SERIAL_VIA_NON_MEMORY_INSTR";
+  case ExecutionMode::ALWAYS_PARALLEL_MISSING_USE_OR_DEF:
+    return "ALWAYS_PARALLEL_MISSING_USE_OR_DEF";
+  case ExecutionMode::PARALLEL_VIA_EXPLICIT_REGS:
+    return "PARALLEL_VIA_EXPLICIT_REGS";
+  }
+  llvm_unreachable("Missing enum case");
+}
+
+static const ExecutionMode kAllExecutionModeBits[] = {
+    ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS,
+    ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS,
+    ExecutionMode::SERIAL_VIA_MEMORY_INSTR,
+    ExecutionMode::SERIAL_VIA_EXPLICIT_REGS,
+    ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR,
+    ExecutionMode::ALWAYS_PARALLEL_MISSING_USE_OR_DEF,
+    ExecutionMode::PARALLEL_VIA_EXPLICIT_REGS,
+};
+
+llvm::ArrayRef<ExecutionMode> getAllExecutionBits() {
+  return kAllExecutionModeBits;
+}
+
+llvm::SmallVector<ExecutionMode, 4>
+getExecutionModeBits(ExecutionMode Execution) {
+  llvm::SmallVector<ExecutionMode, 4> Result;
+  for (const auto Bit : getAllExecutionBits())
+    if ((Execution & Bit) == Bit)
+      Result.push_back(Bit);
+  return Result;
+}
+
 } // namespace exegesis