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| author | Matthew Simpson <mssimpso@codeaurora.org> | 2017-03-02 15:11:20 +0000 |
|---|---|---|
| committer | Matthew Simpson <mssimpso@codeaurora.org> | 2017-03-02 15:11:20 +0000 |
| commit | 1bfa159db981f9e8b941cdf088e3479f426ec927 (patch) | |
| tree | bded2580f06d4b79f466695f4a04668b2f2afb02 /llvm/tools/llvm-dwp/llvm-dwp.cpp | |
| parent | 3ffedcdfa3fdc480899fee8f5cb008b280d8629a (diff) | |
| download | bcm5719-llvm-1bfa159db981f9e8b941cdf088e3479f426ec927.tar.gz bcm5719-llvm-1bfa159db981f9e8b941cdf088e3479f426ec927.zip | |
[ARM/AArch64] Support wide interleaved accesses
This patch teaches (ARM|AArch64)ISelLowering.cpp to match illegal vector types
to interleaved access intrinsics as long as the types are multiples of the
vector register width. A "wide" access will now be mapped to multiple
interleave intrinsics similar to the way in which non-interleaved accesses with
illegal types are legalized into multiple accesses. I'll update the associated
TTI costs (in getInterleavedMemoryOpCost) as a follow-on.
Differential Revision: https://reviews.llvm.org/D29466
llvm-svn: 296750
Diffstat (limited to 'llvm/tools/llvm-dwp/llvm-dwp.cpp')
0 files changed, 0 insertions, 0 deletions
