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| author | Matthias Braun <matze@braunis.de> | 2016-07-06 21:39:33 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2016-07-06 21:39:33 +0000 |
| commit | ad0032a6493002fcc0b3688f53702b0f1762d87b (patch) | |
| tree | 64bd0c2a84f0d65057a3e156a694ca5e568498fc /llvm/tools/llvm-cov/SourceCoverageView.cpp | |
| parent | 332bb5c2364d2d213f768948acbe25b35474cd53 (diff) | |
| download | bcm5719-llvm-ad0032a6493002fcc0b3688f53702b0f1762d87b.tar.gz bcm5719-llvm-ad0032a6493002fcc0b3688f53702b0f1762d87b.zip | |
AArch64: Change modeling of zero cycle zeroing.
On CPUs with the zero cycle zeroing feature enabled "movi v.2d" should
be used to zero a vector register. This was previously done at
instruction selection time, however the register coalescer sometimes
widened multiple vregs to the Q width because of that leading to extra
spills. This patch leaves the decision on how to zero a register to the
AsmPrinter phase where it doesn't affect register allocation anymore.
This patch also sets isAsCheapAsAMove=1 on FMOVS0, FMOVD0.
This fixes http://llvm.org/PR27454, rdar://25866262
Differential Revision: http://reviews.llvm.org/D21826
llvm-svn: 274686
Diffstat (limited to 'llvm/tools/llvm-cov/SourceCoverageView.cpp')
0 files changed, 0 insertions, 0 deletions
