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| author | Jacques Pienaar <jpienaar@google.com> | 2016-11-29 23:01:09 +0000 |
|---|---|---|
| committer | Jacques Pienaar <jpienaar@google.com> | 2016-11-29 23:01:09 +0000 |
| commit | fc13bdd2db3035fc3693fec6aa086db4d1db3e4c (patch) | |
| tree | 79f5be8b63bf49f0aeaa4bf76936dd921e2091de /llvm/test | |
| parent | f57f150b1b4c357ca50291d17f16dfb5dd735527 (diff) | |
| download | bcm5719-llvm-fc13bdd2db3035fc3693fec6aa086db4d1db3e4c.tar.gz bcm5719-llvm-fc13bdd2db3035fc3693fec6aa086db4d1db3e4c.zip | |
[lanai] Manually match 0/-1 with R0/R1.
Summary: Previously 0 and -1 was matched via tablegen rules. But this could cause problems where a physical register was being used where a virtual register was expected (seen in optimizeSelect and TwoAddressInstructionPass). Instead follow AArch64 and match in DAGToDAGISel.
Reviewers: eliben, majnemer
Subscribers: llvm-commits, aemerson
Differential Revision: https://reviews.llvm.org/D27171
llvm-svn: 288215
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/Lanai/constant_multiply.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/Lanai/constant_multiply.ll b/llvm/test/CodeGen/Lanai/constant_multiply.ll index 77c9805e441..80054dbc0f9 100644 --- a/llvm/test/CodeGen/Lanai/constant_multiply.ll +++ b/llvm/test/CodeGen/Lanai/constant_multiply.ll @@ -81,18 +81,18 @@ define i32 @fm8(i32 inreg %a) #0 { } ; CHECK-LABEL: fm9: -; CHECK: sh %r6, 0x3, %r{{[0-9]+}} -; CHECK: sub %r{{[0-9]+}}, %r6, %r{{[0-9]+}} -; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +; CHECK: sub %r0, %r6, %r{{[0-9]+}} +; CHECK: sh %r6, 0x3, %r9 +; CHECK: sub %r{{[0-9]+}}, %r9, %rv define i32 @fm9(i32 inreg %a) #0 { %1 = mul nsw i32 %a, -9 ret i32 %1 } ; CHECK-LABEL: fm10: -; CHECK: sh %r6, 0x3, %r{{[0-9]+}} ; CHECK: sh %r6, 0x1, %r{{[0-9]+}} ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv define i32 @fm10(i32 inreg %a) #0 { %1 = mul nsw i32 %a, -10 |
