[AArch64][SVE] Asm: Support for insert element (INSR) instructions.

Insert general purpose register into shifted vector, e.g.
  insr    z0.s, w0
  insr    z0.d, x0

Insert SIMD&FP scalar register into shifted vector, e.g.
  insr    z0.b, b0
  insr    z0.h, h0
  insr    z0.s, s0
  insr    z0.d, d0

llvm-svn: 336979

2 files changed, 125 insertions, 0 deletions

diff --git a/llvm/test/MC/AArch64/SVE/insr-diagnostics.s b/llvm/test/MC/AArch64/SVE/insr-diagnostics.s
new file mode 100644
index 00000000000..e0ec3e6414c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/insr-diagnostics.s
@@ -0,0 +1,45 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid scalar operand size.
+
+insr    z31.b, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.b, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.h, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.h, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.s, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.s, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.d, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.d, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.b, h0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.b, h0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.h, s0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.h, s0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.s, d0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.s, d0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.d, b0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.d, b0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/insr.s b/llvm/test/MC/AArch64/SVE/insr.s
new file mode 100644
index 00000000000..7e13a1b93fe
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/insr.s
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+insr    z0.b, w0
+// CHECK-INST: insr    z0.b, w0
+// CHECK-ENCODING: [0x00,0x38,0x24,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 24 05 <unknown>
+
+insr    z0.h, w0
+// CHECK-INST: insr    z0.h, w0
+// CHECK-ENCODING: [0x00,0x38,0x64,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 64 05 <unknown>
+
+insr    z0.s, w0
+// CHECK-INST: insr    z0.s, w0
+// CHECK-ENCODING: [0x00,0x38,0xa4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 a4 05 <unknown>
+
+insr    z0.d, x0
+// CHECK-INST: insr    z0.d, x0
+// CHECK-ENCODING: [0x00,0x38,0xe4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 e4 05 <unknown>
+
+insr    z31.b, wzr
+// CHECK-INST: insr    z31.b, wzr
+// CHECK-ENCODING: [0xff,0x3b,0x24,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 24 05 <unknown>
+
+insr    z31.h, wzr
+// CHECK-INST: insr    z31.h, wzr
+// CHECK-ENCODING: [0xff,0x3b,0x64,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 64 05 <unknown>
+
+insr    z31.s, wzr
+// CHECK-INST: insr    z31.s, wzr
+// CHECK-ENCODING: [0xff,0x3b,0xa4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b a4 05 <unknown>
+
+insr    z31.d, xzr
+// CHECK-INST: insr    z31.d, xzr
+// CHECK-ENCODING: [0xff,0x3b,0xe4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b e4 05 <unknown>
+
+insr    z31.b, b31
+// CHECK-INST: insr    z31.b, b31
+// CHECK-ENCODING: [0xff,0x3b,0x34,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 34 05 <unknown>
+
+insr    z31.h, h31
+// CHECK-INST: insr    z31.h, h31
+// CHECK-ENCODING: [0xff,0x3b,0x74,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 74 05 <unknown>
+
+insr    z31.s, s31
+// CHECK-INST: insr    z31.s, s31
+// CHECK-ENCODING: [0xff,0x3b,0xb4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b b4 05 <unknown>
+
+insr    z31.d, d31
+// CHECK-INST: insr    z31.d, d31
+// CHECK-ENCODING: [0xff,0x3b,0xf4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b f4 05 <unknown>