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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-14 18:32:05 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-14 18:32:05 +0000 |
| commit | f620a575bf0cad9935bd307e04414f9f7f186399 (patch) | |
| tree | 9d62c90eedb001b04c45148181538d57e52b356f /llvm/test | |
| parent | 05ce999134d9358cb781c9d8e64af0688d1a1e94 (diff) | |
| download | bcm5719-llvm-f620a575bf0cad9935bd307e04414f9f7f186399.tar.gz bcm5719-llvm-f620a575bf0cad9935bd307e04414f9f7f186399.zip | |
R600/SI: Fix broken check lines
llvm-svn: 217736
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/R600/unaligned-load-store.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/R600/unaligned-load-store.ll b/llvm/test/CodeGen/R600/unaligned-load-store.ll index 7df7ba00d54..cca7df5f34e 100644 --- a/llvm/test/CodeGen/R600/unaligned-load-store.ll +++ b/llvm/test/CodeGen/R600/unaligned-load-store.ll @@ -80,7 +80,7 @@ define void @store_lds_i64_align_4(i64 addrspace(3)* %out, i64 %val) #0 { } ; SI-LABEL: @store_lds_i64_align_4_with_offset -; DS_WRITE_B32 v[{{[0-9]+}}], v[{{[0-9]+}}], v{{[0-9]}}, 0x9, 0x9 +; SI: DS_WRITE2_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 0x8, 0x9 ; SI: S_ENDPGM define void @store_lds_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 { %ptr = getelementptr i64 addrspace(3)* %out, i32 4 @@ -90,7 +90,7 @@ define void @store_lds_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 { ; SI-LABEL: @store_lds_i64_align_4_with_split_offset ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits -; DS_WRITE_B32 v[{{[0-9]+}}], v[{{[0-9]+}}], v{{[0-9]}}, 0x0, 0x1 +; SI: DS_WRITE2_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]}}, 0x0, 0x1 ; SI: S_ENDPGM define void @store_lds_i64_align_4_with_split_offset(i64 addrspace(3)* %out) #0 { %ptr = bitcast i64 addrspace(3)* %out to i32 addrspace(3)* |
