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| author | Andrew Trick <atrick@apple.com> | 2010-10-21 03:40:16 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2010-10-21 03:40:16 +0000 |
| commit | f4ebec03e01800ada58f02716a2941d0c6712bd4 (patch) | |
| tree | 3d9588f43621ff9a12f79c8be133f3df9c3d0e62 /llvm/test | |
| parent | 078db00f1d1c8bec03c00133d114507d27d870b3 (diff) | |
| download | bcm5719-llvm-f4ebec03e01800ada58f02716a2941d0c6712bd4.tar.gz bcm5719-llvm-f4ebec03e01800ada58f02716a2941d0c6712bd4.zip | |
putback r116983 and fix simple-fp-encoding.ll tests
llvm-svn: 116992
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fmscs.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/reg_sequence.ll | 3 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/simple-fp-encoding.ll | 24 |
3 files changed, 15 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/ARM/fmscs.ll b/llvm/test/CodeGen/ARM/fmscs.ll index 103ce334519..19359a1ae6b 100644 --- a/llvm/test/CodeGen/ARM/fmscs.ll +++ b/llvm/test/CodeGen/ARM/fmscs.ll @@ -19,6 +19,6 @@ entry: ; NFP0: vnmls.f32 s2, s1, s0 ; CORTEXA8: test: -; CORTEXA8: vnmls.f32 s2, s1, s0 +; CORTEXA8: vnmls.f32 s1, s2, s0 ; CORTEXA9: test: ; CORTEXA9: vnmls.f32 s0, s1, s2 diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll index 1a95897c26c..390955472ec 100644 --- a/llvm/test/CodeGen/ARM/reg_sequence.ll +++ b/llvm/test/CodeGen/ARM/reg_sequence.ll @@ -75,7 +75,8 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { ; CHECK: t3: ; CHECK: vld3.8 ; CHECK: vmul.i8 -; CHECK-NOT: vmov +; CHECK: vmov r +; CHECK-NOT: vmov d ; CHECK: vst3.8 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1] diff --git a/llvm/test/MC/ARM/simple-fp-encoding.ll b/llvm/test/MC/ARM/simple-fp-encoding.ll index 230fc87df75..3e05b0ab688 100644 --- a/llvm/test/MC/ARM/simple-fp-encoding.ll +++ b/llvm/test/MC/ARM/simple-fp-encoding.ll @@ -269,7 +269,7 @@ entry: define float @f91(float %a, float %b, float %c) nounwind readnone { entry: ; CHECK: f91 -; CHECK: vmla.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x00,0xee] +; CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee] %mul = fmul float %a, %b %add = fadd float %mul, %c ret float %add @@ -287,7 +287,7 @@ entry: define float @f93(float %a, float %b, float %c) nounwind readnone { entry: ; CHECK: f93 -; CHECK: vmls.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x00,0xee] +; CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee] %mul = fmul float %a, %b %sub = fsub float %c, %mul ret float %sub @@ -306,7 +306,7 @@ entry: define float @f95(float %a, float %b, float %c) nounwind readnone { entry: ; CHECK: f95 -; CHECK: vnmla.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x10,0xee] +; CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee] %mul = fmul float %a, %b %sub = fsub float -0.000000e+00, %mul %sub3 = fsub float %sub, %c @@ -325,7 +325,7 @@ entry: define float @f97(float %a, float %b, float %c) nounwind readnone { entry: ; CHECK: f97 -; CHECK: vnmls.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x10,0xee] +; CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] %mul = fmul float %a, %b %sub = fsub float %mul, %c ret float %sub @@ -404,10 +404,10 @@ entry: define void @f104(float %a, float %b, float %c, float %d, float %e, float %f) nounwind { entry: ; CHECK: f104 -; CHECK: vmov s2, r0 @ encoding: [0x10,0x0a,0x01,0xee] -; CHECK: vmov s3, r1 @ encoding: [0x90,0x1a,0x01,0xee] -; CHECK: vmov s4, r2 @ encoding: [0x10,0x2a,0x02,0xee] -; CHECK: vmov s5, r3 @ encoding: [0x90,0x3a,0x02,0xee] +; CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee] +; CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee] +; CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee] +; CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee] %conv = fptosi float %a to i32 %conv2 = fptosi float %b to i32 %conv4 = fptosi float %c to i32 @@ -415,10 +415,10 @@ entry: %conv8 = fptosi float %e to i32 %conv10 = fptosi float %f to i32 tail call void @g104(i32 %conv, i32 %conv2, i32 %conv4, i32 %conv6, i32 %conv8, i32 %conv10) nounwind -; CHECK: vmov r0, s2 @ encoding: [0x10,0x0a,0x11,0xee] -; CHECK: vmov r1, s3 @ encoding: [0x90,0x1a,0x11,0xee] -; CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee] -; CHECK: vmov r3, s5 @ encoding: [0x90,0x3a,0x12,0xee] +; CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee] +; CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee] +; CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee] +; CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee] ret void } |

