[SystemZ] Make better use of VLDEB

We already have special code (DAG combine support for FP_ROUND)
to recognize cases where we an use a vector version of VLEDB to
perform two floating-point truncates in parallel, but equivalent
support for VLEDB (vector floating-point extends) has been
missing so far.  This patch adds corresponding DAG combine
support for FP_EXTEND.

llvm-svn: 349746

1 files changed, 14 insertions, 3 deletions

diff --git a/llvm/test/CodeGen/SystemZ/vec-conv-02.ll b/llvm/test/CodeGen/SystemZ/vec-conv-02.ll
index ab84389f3c8..d4c0f726418 100644
--- a/llvm/test/CodeGen/SystemZ/vec-conv-02.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-conv-02.ll
@@ -15,19 +15,30 @@ define void @f1(<2 x double> %val, <2 x float> *%ptr) {
 ; Test conversion of an f64 in a vector register to an f32.
 define float @f2(<2 x double> %vec) {
 ; CHECK-LABEL: f2:
-; CHECK: wledb %f0, %v24
+; CHECK: wledb %f0, %v24, 0, 0
 ; CHECK: br %r14
   %scalar = extractelement <2 x double> %vec, i32 0
   %ret = fptrunc double %scalar to float
   ret float %ret
 }
 
-; Test conversion of an f32 in a vector register to an f64.
-define double @f3(<4 x float> %vec) {
+; Test cases where even elements of a v4f32 are converted to f64s.
+define <2 x double> @f3(<4 x float> %vec) {
 ; CHECK-LABEL: f3:
+; CHECK: vldeb %v24, {{%v[0-9]+}}
+; CHECK: br %r14
+  %shuffle = shufflevector <4 x float> %vec, <4 x float> undef, <2 x i32> <i32 0, i32 2>
+  %res = fpext <2 x float> %shuffle to <2 x double>
+  ret <2 x double> %res
+}
+
+; Test conversion of an f32 in a vector register to an f64.
+define double @f4(<4 x float> %vec) {
+; CHECK-LABEL: f4:
 ; CHECK: wldeb %f0, %v24
 ; CHECK: br %r14
   %scalar = extractelement <4 x float> %vec, i32 0
   %ret = fpext float %scalar to double
   ret double %ret
 }
+