[AArch64][SVE] Asm: FP fused multiply-add/subtract instructions.

This patch adds support for the following instructions:

  FMLA    mul-add, writing addend                (Zda =  Zda +   Zn * Zm)
  FNMLA   negated mul-add, writing addend        (Zda = -Zda +  -Zn * Zm)

  FMLS    mul-sub, writing addend                (Zda =  Zda +  -Zn * Zm)
  FNMLS   negated mul-sub, writing addend        (Zda = -Zda +   Zn * Zm)

  FMAD    mul-add, writing multiplicant          (Zdn =  Za  +  Zdn * Zm)
  FNMAD   negated mul-add, writing multiplicant  (Zdn = -Za  + -Zdn * Zm)

  FMSB    mul-sub, writing multiplicant          (Zdn =  Za  + -Zdn * Zm)
  FNMSB   negated mul-sub, writing multiplicant  (Zdn = -Za  +  Zdn * Zm)

llvm-svn: 337282

16 files changed, 576 insertions, 0 deletions

diff --git a/llvm/test/MC/AArch64/SVE/fmad-diagnostics.s b/llvm/test/MC/AArch64/SVE/fmad-diagnostics.s
new file mode 100644
index 00000000000..ab9301c97c5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmad-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fmad z0.h, p8/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmad z0.h, p8/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmad z0.s, p7/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmad z0.s, p7/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmad z0.b, p7/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmad z0.b, p7/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Element index is not allowed
+
+fmad z0.h, p7/m, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: fmad z0.h, p7/m, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fmad.s b/llvm/test/MC/AArch64/SVE/fmad.s
new file mode 100644
index 00000000000..dbcec437c32
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmad.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmad z0.h, p7/m, z1.h, z31.h
+// CHECK-INST: fmad	z0.h, p7/m, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x9c,0x7f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 9c 7f 65 <unknown>
+
+fmad z0.s, p7/m, z1.s, z31.s
+// CHECK-INST: fmad	z0.s, p7/m, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x9c,0xbf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 9c bf 65 <unknown>
+
+fmad z0.d, p7/m, z1.d, z31.d
+// CHECK-INST: fmad	z0.d, p7/m, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x9c,0xff,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 9c ff 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fmla-diagnostics.s b/llvm/test/MC/AArch64/SVE/fmla-diagnostics.s
new file mode 100644
index 00000000000..43b452f1e7b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmla-diagnostics.s
@@ -0,0 +1,72 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fmla z0.h, p8/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmla z0.h, p8/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmla z0.s, p7/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmla z0.s, p7/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmla z0.h, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
+// CHECK-NEXT: fmla z0.h, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla z0.s, z1.s, z8.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s
+// CHECK-NEXT: fmla z0.s, z1.s, z8.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla z0.d, z1.d, z16.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
+// CHECK-NEXT: fmla z0.d, z1.d, z16.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element index
+
+fmla z0.h, z1.h, z2.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmla z0.h, z1.h, z2.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla z0.h, z1.h, z2.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmla z0.h, z1.h, z2.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla z0.s, z1.s, z2.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: fmla z0.s, z1.s, z2.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla z0.s, z1.s, z2.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: fmla z0.s, z1.s, z2.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla z0.d, z1.d, z2.d[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: fmla z0.d, z1.d, z2.d[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla z0.d, z1.d, z2.d[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: fmla z0.d, z1.d, z2.d[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fmla.s b/llvm/test/MC/AArch64/SVE/fmla.s
new file mode 100644
index 00000000000..3b1f54c3759
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmla.s
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmla z0.h, p7/m, z1.h, z31.h
+// CHECK-INST: fmla	z0.h, p7/m, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x1c,0x7f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 1c 7f 65 <unknown>
+
+fmla z0.s, p7/m, z1.s, z31.s
+// CHECK-INST: fmla	z0.s, p7/m, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x1c,0xbf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 1c bf 65 <unknown>
+
+fmla z0.d, p7/m, z1.d, z31.d
+// CHECK-INST: fmla	z0.d, p7/m, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x1c,0xff,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 1c ff 65 <unknown>
+
+fmla z0.h, z1.h, z7.h[7]
+// CHECK-INST: fmla	z0.h, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0x00,0x7f,0x64]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 7f 64 <unknown>
+
+fmla z0.s, z1.s, z7.s[3]
+// CHECK-INST: fmla	z0.s, z1.s, z7.s[3]
+// CHECK-ENCODING: [0x20,0x00,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 bf 64 <unknown>
+
+fmla z0.d, z1.d, z7.d[1]
+// CHECK-INST: fmla	z0.d, z1.d, z7.d[1]
+// CHECK-ENCODING: [0x20,0x00,0xf7,0x64]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 f7 64 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fmls-diagnostics.s b/llvm/test/MC/AArch64/SVE/fmls-diagnostics.s
new file mode 100644
index 00000000000..f7734f8fe9a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmls-diagnostics.s
@@ -0,0 +1,72 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fmls z0.h, p8/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmls z0.h, p8/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmls z0.s, p7/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmls z0.s, p7/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmls z0.h, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
+// CHECK-NEXT: fmls z0.h, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls z0.s, z1.s, z8.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s
+// CHECK-NEXT: fmls z0.s, z1.s, z8.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls z0.d, z1.d, z16.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
+// CHECK-NEXT: fmls z0.d, z1.d, z16.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element index
+
+fmls z0.h, z1.h, z2.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmls z0.h, z1.h, z2.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls z0.h, z1.h, z2.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmls z0.h, z1.h, z2.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls z0.s, z1.s, z2.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: fmls z0.s, z1.s, z2.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls z0.s, z1.s, z2.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: fmls z0.s, z1.s, z2.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls z0.d, z1.d, z2.d[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: fmls z0.d, z1.d, z2.d[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls z0.d, z1.d, z2.d[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: fmls z0.d, z1.d, z2.d[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fmls.s b/llvm/test/MC/AArch64/SVE/fmls.s
new file mode 100644
index 00000000000..c337d8c3aec
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmls.s
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmls z0.h, p7/m, z1.h, z31.h
+// CHECK-INST: fmls	z0.h, p7/m, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x3c,0x7f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 3c 7f 65 <unknown>
+
+fmls z0.s, p7/m, z1.s, z31.s
+// CHECK-INST: fmls	z0.s, p7/m, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x3c,0xbf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 3c bf 65 <unknown>
+
+fmls z0.d, p7/m, z1.d, z31.d
+// CHECK-INST: fmls	z0.d, p7/m, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x3c,0xff,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 3c ff 65 <unknown>
+
+fmls z0.h, z1.h, z7.h[7]
+// CHECK-INST: fmls	z0.h, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0x04,0x7f,0x64]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 7f 64 <unknown>
+
+fmls z0.s, z1.s, z7.s[3]
+// CHECK-INST: fmls	z0.s, z1.s, z7.s[3]
+// CHECK-ENCODING: [0x20,0x04,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 bf 64 <unknown>
+
+fmls z0.d, z1.d, z7.d[1]
+// CHECK-INST: fmls	z0.d, z1.d, z7.d[1]
+// CHECK-ENCODING: [0x20,0x04,0xf7,0x64]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 f7 64 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fmsb-diagnostics.s b/llvm/test/MC/AArch64/SVE/fmsb-diagnostics.s
new file mode 100644
index 00000000000..df4dbe54fb1
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmsb-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fmsb z0.h, p8/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmsb z0.h, p8/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmsb z0.s, p7/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmsb z0.s, p7/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmsb z0.b, p7/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmsb z0.b, p7/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Element index is not allowed
+
+fmsb z0.h, p7/m, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: fmsb z0.h, p7/m, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fmsb.s b/llvm/test/MC/AArch64/SVE/fmsb.s
new file mode 100644
index 00000000000..4e34073ff10
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmsb.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmsb z0.h, p7/m, z1.h, z31.h
+// CHECK-INST: fmsb	z0.h, p7/m, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xbc,0x7f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 bc 7f 65 <unknown>
+
+fmsb z0.s, p7/m, z1.s, z31.s
+// CHECK-INST: fmsb	z0.s, p7/m, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xbc,0xbf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 bc bf 65 <unknown>
+
+fmsb z0.d, p7/m, z1.d, z31.d
+// CHECK-INST: fmsb	z0.d, p7/m, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xbc,0xff,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 bc ff 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fnmad-diagnostics.s b/llvm/test/MC/AArch64/SVE/fnmad-diagnostics.s
new file mode 100644
index 00000000000..8d12d89d631
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fnmad-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fnmad z0.h, p8/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fnmad z0.h, p8/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fnmad z0.s, p7/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fnmad z0.s, p7/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fnmad z0.b, p7/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fnmad z0.b, p7/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Element index is not allowed
+
+fnmad z0.h, p7/m, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: fnmad z0.h, p7/m, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fnmad.s b/llvm/test/MC/AArch64/SVE/fnmad.s
new file mode 100644
index 00000000000..6bb736c9eb4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fnmad.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fnmad z0.h, p7/m, z1.h, z31.h
+// CHECK-INST: fnmad	z0.h, p7/m, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xdc,0x7f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 dc 7f 65 <unknown>
+
+fnmad z0.s, p7/m, z1.s, z31.s
+// CHECK-INST: fnmad	z0.s, p7/m, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xdc,0xbf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 dc bf 65 <unknown>
+
+fnmad z0.d, p7/m, z1.d, z31.d
+// CHECK-INST: fnmad	z0.d, p7/m, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xdc,0xff,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 dc ff 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fnmla-diagnostics.s b/llvm/test/MC/AArch64/SVE/fnmla-diagnostics.s
new file mode 100644
index 00000000000..df9053c4b9d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fnmla-diagnostics.s
@@ -0,0 +1,28 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fnmla z0.h, p8/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fnmla z0.h, p8/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fnmla z0.s, p7/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fnmla z0.s, p7/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Element index is not allowed
+
+fnmla z0.h, p7/m, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: fnmla z0.h, p7/m, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fnmla.s b/llvm/test/MC/AArch64/SVE/fnmla.s
new file mode 100644
index 00000000000..49d443f2610
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fnmla.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fnmla z0.h, p7/m, z1.h, z31.h
+// CHECK-INST: fnmla	z0.h, p7/m, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x5c,0x7f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 5c 7f 65 <unknown>
+
+fnmla z0.s, p7/m, z1.s, z31.s
+// CHECK-INST: fnmla	z0.s, p7/m, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x5c,0xbf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 5c bf 65 <unknown>
+
+fnmla z0.d, p7/m, z1.d, z31.d
+// CHECK-INST: fnmla	z0.d, p7/m, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x5c,0xff,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 5c ff 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fnmls-diagnostics.s b/llvm/test/MC/AArch64/SVE/fnmls-diagnostics.s
new file mode 100644
index 00000000000..4136cb0f50e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fnmls-diagnostics.s
@@ -0,0 +1,28 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fnmls z0.h, p8/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fnmls z0.h, p8/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fnmls z0.s, p7/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fnmls z0.s, p7/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Element index is not allowed
+
+fnmls z0.h, p7/m, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: fnmls z0.h, p7/m, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fnmls.s b/llvm/test/MC/AArch64/SVE/fnmls.s
new file mode 100644
index 00000000000..438fbaeed6d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fnmls.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fnmls z0.h, p7/m, z1.h, z31.h
+// CHECK-INST: fnmls	z0.h, p7/m, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x7c,0x7f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 7c 7f 65 <unknown>
+
+fnmls z0.s, p7/m, z1.s, z31.s
+// CHECK-INST: fnmls	z0.s, p7/m, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x7c,0xbf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 7c bf 65 <unknown>
+
+fnmls z0.d, p7/m, z1.d, z31.d
+// CHECK-INST: fnmls	z0.d, p7/m, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x7c,0xff,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 7c ff 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fnmsb-diagnostics.s b/llvm/test/MC/AArch64/SVE/fnmsb-diagnostics.s
new file mode 100644
index 00000000000..51981dda9a4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fnmsb-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fnmsb z0.h, p8/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fnmsb z0.h, p8/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fnmsb z0.s, p7/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fnmsb z0.s, p7/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fnmsb z0.b, p7/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fnmsb z0.b, p7/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Element index is not allowed
+
+fnmsb z0.h, p7/m, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: fnmsb z0.h, p7/m, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fnmsb.s b/llvm/test/MC/AArch64/SVE/fnmsb.s
new file mode 100644
index 00000000000..f06de48afbf
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fnmsb.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fnmsb z0.h, p7/m, z1.h, z31.h
+// CHECK-INST: fnmsb	z0.h, p7/m, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xfc,0x7f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fc 7f 65 <unknown>
+
+fnmsb z0.s, p7/m, z1.s, z31.s
+// CHECK-INST: fnmsb	z0.s, p7/m, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xfc,0xbf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fc bf 65 <unknown>
+
+fnmsb z0.d, p7/m, z1.d, z31.d
+// CHECK-INST: fnmsb	z0.d, p7/m, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xfc,0xff,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fc ff 65 <unknown>