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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-10 00:29:55 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-10 00:29:55 +0000 |
| commit | f0c862594b77b131dab77d7b8edcc86ab23660dc (patch) | |
| tree | 1bd70c12e3d99c2062573e150473bd77080871ce /llvm/test | |
| parent | 618b330dd006b731e07129d4c971eb905707133d (diff) | |
| download | bcm5719-llvm-f0c862594b77b131dab77d7b8edcc86ab23660dc.tar.gz bcm5719-llvm-f0c862594b77b131dab77d7b8edcc86ab23660dc.zip | |
AMDGPU: Fix vintrp disassembly
llvm-svn: 289292
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/missing_op.txt | 5 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/vintrp.txt | 49 |
2 files changed, 49 insertions, 5 deletions
diff --git a/llvm/test/MC/Disassembler/AMDGPU/missing_op.txt b/llvm/test/MC/Disassembler/AMDGPU/missing_op.txt deleted file mode 100644 index 010da5fd280..00000000000 --- a/llvm/test/MC/Disassembler/AMDGPU/missing_op.txt +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble < %s | FileCheck %s -check-prefix=VI - -#TODO: this test will fail when we fix v_interp_p2_f32 signature, remove it then -#VI: v_interp_p2_f32 v7, 16, /*Missing OP3*/, /*Missing OP4*/ -0xd4 0x41 0x1d 0xd4 diff --git a/llvm/test/MC/Disassembler/AMDGPU/vintrp.txt b/llvm/test/MC/Disassembler/AMDGPU/vintrp.txt new file mode 100644 index 00000000000..881f09be407 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/vintrp.txt @@ -0,0 +1,49 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble < %s | FileCheck %s -check-prefix=VI + +#VI: v_interp_p1_f32 v7, v212, 1, 16 +0xd4 0x41 0x1c 0xd4 + +#VI: v_interp_p2_f32 v7, v212, 1, 16 +0xd4 0x41 0x1d 0xd4 + +#VI: v_interp_mov_f32 v7, invalid_param_212, 1, 16 +0xd4 0x41 0x1e 0xd4 + +#VI: v_interp_mov_f32 v7, p10, 1, 16 +0x00 0x41 0x1e 0xd4 + +#VI: v_interp_mov_f32 v7, p20, 1, 16 +0x01 0x41 0x1e 0xd4 + +#VI: v_interp_mov_f32 v7, p0, 1, 16 +0x02 0x41 0x1e 0xd4 + +#VI: v_interp_mov_f32 v7, invalid_param_3, 1, 16 +0x03 0x41 0x1e 0xd4 + +# VI: v_interp_p1_f32 v0, v0, 0, 0 +0x00 0x00 0x00 0xd4 + +# VI: v_interp_p1_f32 v0, v0, 0, 0 +0x00 0x00 0x00 0xd4 + +# VI: v_interp_p1_f32 v0, v1, 0, 0 +0x01 0x00 0x00 0xd4 + +# VI: v_interp_p1_f32 v0, v1, 3, 0 +0x01 0x03 0x00 0xd4 + +# VI: v_interp_p2_f32 v0, v1, 0, 0 +0x01 0x00 0x01 0xd4 + +# VI: v_interp_mov_f32 v0, p20, 0, 0 +0x01 0x00 0x02 0xd4 + +#VI: v_interp_p2_f32 v0, v1, 0, 63 +0x01 0xfc 0x01 0xd4 + +#VI: v_interp_p2_f32 v0, v1, 0, 63 +0x01 0xfc 0x01 0xd4 + +#VI: v_interp_p2_f32 v0, v1, 3, 63 +0x01 0xff 0x01 0xd4 |
