[AMDGPU] calling conventions for AMDPAL OS type

Summary:
This commit adds comments on how the AMDPAL OS type overloads the
existing AMDGPU_ calling conventions used by Mesa, and adds a couple of
new ones.

Reviewers: arsenm, nhaehnle, dstuttard

Subscribers: mehdi_amini, kzhuravl, wdng, yaxunl, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D37752

llvm-svn: 314502

9 files changed, 149 insertions, 1 deletions

diff --git a/llvm/test/Bitcode/compatibility.ll b/llvm/test/Bitcode/compatibility.ll
index 367158d206d..7d4167f4cb0 100644
--- a/llvm/test/Bitcode/compatibility.ll
+++ b/llvm/test/Bitcode/compatibility.ll
@@ -476,6 +476,14 @@ declare cc93 void @f.cc93()
 ; CHECK: declare amdgpu_hs void @f.cc93()
 declare amdgpu_hs void @f.amdgpu_hs()
 ; CHECK: declare amdgpu_hs void @f.amdgpu_hs()
+declare cc95 void @f.cc95()
+; CHECK: declare amdgpu_ls void @f.cc95()
+declare amdgpu_ls void @f.amdgpu_ls()
+; CHECK: declare amdgpu_ls void @f.amdgpu_ls()
+declare cc96 void @f.cc96()
+; CHECK: declare amdgpu_es void @f.cc96()
+declare amdgpu_es void @f.amdgpu_es()
+; CHECK: declare amdgpu_es void @f.amdgpu_es()
 declare cc1023 void @f.cc1023()
 ; CHECK: declare cc1023 void @f.cc1023()
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
new file mode 100644
index 00000000000..d722a4c2f38
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
@@ -0,0 +1,13 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  47176
+; GCN-LABEL: {{^}}cs_amdpal:
+define amdgpu_cs half @cs_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-es.ll b/llvm/test/CodeGen/AMDGPU/amdpal-es.ll
new file mode 100644
index 00000000000..fa976850f9d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-es.ll
@@ -0,0 +1,13 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+; amdpal pixel shader: check for 45864 (SPI_SHADER_PGM_RSRC1_ES) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  45864
+; GCN-LABEL: {{^}}es_amdpal:
+define amdgpu_es half @es_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
new file mode 100644
index 00000000000..d34c0f22f5a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal pixel shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  45608
+; GCN-LABEL: {{^}}gs_amdpal:
+define amdgpu_gs half @gs_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
new file mode 100644
index 00000000000..eeaacf302c0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal pixel shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  46120
+; GCN-LABEL: {{^}}hs_amdpal:
+define amdgpu_hs half @hs_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll b/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
new file mode 100644
index 00000000000..e4624d04a96
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
@@ -0,0 +1,13 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+; amdpal pixel shader: check for 46376 (SPI_SHADER_PGM_RSRC1_LS) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  46376
+; GCN-LABEL: {{^}}ls_amdpal:
+define amdgpu_ls half @ls_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-ps.ll b/llvm/test/CodeGen/AMDGPU/amdpal-ps.ll
new file mode 100644
index 00000000000..89a3d63774a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-ps.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  45096
+; GCN-LABEL: {{^}}ps_amdpal:
+define amdgpu_ps half @ps_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
new file mode 100644
index 00000000000..942b4581772
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal pixel shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  45352
+; GCN-LABEL: {{^}}vs_amdpal:
+define amdgpu_vs half @vs_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index 9bf94a1f2da..5a6fe9ac190 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -76,4 +76,49 @@ define amdgpu_kernel void @call_fastcc() #0 {
   ret void
 }
 
-attributes #0 = { nounwind noinline }
\ No newline at end of file
+; Mesa compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  47176
+; GCN-LABEL: {{^}}cs_mesa:
+define amdgpu_cs half @cs_mesa(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Mesa pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  45096
+; GCN-LABEL: {{^}}ps_mesa:
+define amdgpu_ps half @ps_mesa(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Mesa vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  45352
+; GCN-LABEL: {{^}}vs_mesa:
+define amdgpu_vs half @vs_mesa(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Mesa geometry shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  45608
+; GCN-LABEL: {{^}}gs_mesa:
+define amdgpu_gs half @gs_mesa(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Mesa hull shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config
+; GCN-LABEL: .AMDGPU.config
+; GCN: .long  46120
+; GCN-LABEL: {{^}}hs_mesa:
+define amdgpu_hs half @hs_mesa(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+attributes #0 = { nounwind noinline }