[AMDGPU] Added MsgPack format PAL metadata

Summary:
PAL metadata now supports both the old linear reg=val pairs format and
the new MsgPack format.

The MsgPack format uses YAML as its textual representation. On output to
YAML, a mnemonic name is provided for some hardware registers.

Differential Revision: https://reviews.llvm.org/D57028

Change-Id: I2bbaabaaca4b3574f7e03b80fbef7c7a69d06a94
llvm-svn: 356591

9 files changed, 217 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll
new file mode 100644
index 00000000000..16caa645dc7
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
+; GCN-LABEL: {{^}}cs_amdpal:
+; GCN: .amdgpu_pal_metadata
+; GCN: 0x2e12 (COMPUTE_PGM_RSRC1)
+define amdgpu_cs half @cs_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Force MsgPack format metadata
+!amdgpu.pal.metadata.msgpack = !{!0}
+!0 = !{!""}
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll
new file mode 100644
index 00000000000..898f7525ee4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
+; GCN-LABEL: {{^}}es_amdpal:
+; GCN: .amdgpu_pal_metadata
+; GCN: 0x2cca (SPI_SHADER_PGM_RSRC1_ES)
+define amdgpu_es half @es_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Force MsgPack format metadata
+!amdgpu.pal.metadata.msgpack = !{!0}
+!0 = !{!""}
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll
new file mode 100644
index 00000000000..16d79c15e31
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
+; GCN-LABEL: {{^}}gs_amdpal:
+; GCN: .amdgpu_pal_metadata
+; GCN: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS)
+define amdgpu_gs half @gs_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Force MsgPack format metadata
+!amdgpu.pal.metadata.msgpack = !{!0}
+!0 = !{!""}
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll
new file mode 100644
index 00000000000..509e196a01d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
+; GCN-LABEL: {{^}}hs_amdpal:
+; GCN: .amdgpu_pal_metadata
+; GCN: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS)
+define amdgpu_hs half @hs_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Force MsgPack format metadata
+!amdgpu.pal.metadata.msgpack = !{!0}
+!0 = !{!""}
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll
new file mode 100644
index 00000000000..aa59bbac0e8
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
+; GCN-LABEL: {{^}}ls_amdpal:
+; GCN: .amdgpu_pal_metadata
+; GCN: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS)
+define amdgpu_ls half @ls_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Force MsgPack format metadata
+!amdgpu.pal.metadata.msgpack = !{!0}
+!0 = !{!""}
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll
new file mode 100644
index 00000000000..f5489dc43b8
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal
+; metadata. Check for 0x2c0b (SPI_SHADER_PGM_RSRC2_PS) in pal metadata, and
+; it has a value starting 0x42 as it is set to 0x42000000 in the metadata
+; below. Also check that .internal_pipeline_hash is propagated.
+; GCN-LABEL: {{^}}ps_amdpal:
+; GCN: .amdgpu_pal_metadata
+; GCN:         .internal_pipeline_hash:
+; GCN-NEXT:      - 0x123456789abcdef0
+; GCN-NEXT:      - 0xfedcba9876543210
+; GCN:         .registers:
+; GCN:           0x2c0a (SPI_SHADER_PGM_RSRC1_PS):
+; GCN:           0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42
+define amdgpu_ps half @ps_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; amdgpu.pal.metadata.msgpack represents this:
+;
+; 	.amdgpu_pal_metadata
+; ---
+; amdpal.pipelines: 
+;   - .internal_pipeline_hash:
+;       - 0x123456789abcdef0
+;       - 0xfedcba9876543210
+;     .registers:
+;       0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000
+; ...
+; 	.end_amdgpu_pal_metadata
+
+!amdgpu.pal.metadata.msgpack = !{!0}
+!0 = !{!"\81\b0\61\6d\64\70\61\6c\2e\70\69\70\65\6c\69\6e\65\73\91\82\b7\2e\69\6e\74\65\72\6e\61\6c\5f\70\69\70\65\6c\69\6e\65\5f\68\61\73\68\92\cf\12\34\56\78\9a\bc\de\f0\cf\fe\dc\ba\98\76\54\32\10\aa\2e\72\65\67\69\73\74\65\72\73\81\cd\2c\0b\ce\42\00\00\00"};
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll
new file mode 100644
index 00000000000..4794f248628
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; This pixel shader does not use the result of its interpolation, so it would
+; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests
+; the workaround that ensures that an interpolation mode is also set in PSEnable.
+; GCN-LABEL: {{^}}amdpal_psenable:
+; GCN: .amdgpu_pal_metadata
+; GCN: 0xa1b3 (SPI_PS_INPUT_ENA): 0x2
+; GCN: 0xa1b4 (SPI_PS_INPUT_ADDR): 0x2
+define amdgpu_ps void @amdpal_psenable(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <2 x float> %pos) #6 {
+  %inst23 = extractelement <2 x float> %pos, i32 0
+  %inst24 = extractelement <2 x float> %pos, i32 1
+  %inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0)
+  %inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0)
+  ret void
+}
+
+declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2
+declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2
+
+attributes #6 = { nounwind "InitialPSInputAddr"="2" }
+
+; Force MsgPack format metadata
+!amdgpu.pal.metadata.msgpack = !{!0}
+!0 = !{!""}
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll
new file mode 100644
index 00000000000..c8fd9a9f2de
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
+; GCN-LABEL: {{^}}vs_amdpal:
+; GCN: .amdgpu_pal_metadata
+; GCN: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS)
+define amdgpu_vs half @vs_amdpal(half %arg0) {
+  %add = fadd half %arg0, 1.0
+  ret half %add
+}
+
+; Force MsgPack format metadata
+!amdgpu.pal.metadata.msgpack = !{!0}
+!0 = !{!""}
diff --git a/llvm/test/MC/AMDGPU/pal-msgpack.s b/llvm/test/MC/AMDGPU/pal-msgpack.s
new file mode 100644
index 00000000000..52a967c8005
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/pal-msgpack.s
@@ -0,0 +1,60 @@
+// RUN: llvm-mc -triple amdgcn--amdpal -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM
+// RUN: llvm-mc -filetype=obj -triple amdgcn--amdpal -mcpu=kaveri -show-encoding %s | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
+
+	.amdgpu_pal_metadata
+---
+amdpal.pipelines: 
+  - .hardware_stages: 
+      .ps:             
+        .entry_point:    ps_amdpal
+        .scratch_memory_size: 0
+        .sgpr_count:     0x1
+        .vgpr_count:     0x1
+    .internal_pipeline_hash: 
+      - 0x123456789abcdef0
+      - 0xfedcba9876543210
+    .registers:      
+      0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0
+      0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000
+      0xa1b3 (SPI_PS_INPUT_ENA): 0x1
+      0xa1b4 (SPI_PS_INPUT_ADDR): 0x1
+...
+	.end_amdgpu_pal_metadata
+
+// ASM: 	.amdgpu_pal_metadata
+// ASM: ---
+// ASM: amdpal.pipelines: 
+// ASM:   - .hardware_stages: 
+// ASM:       .ps:             
+// ASM:         .entry_point:    ps_amdpal
+// ASM:         .scratch_memory_size: 0
+// ASM:         .sgpr_count:     0x1
+// ASM:         .vgpr_count:     0x1
+// ASM:     .internal_pipeline_hash: 
+// ASM:       - 0x123456789abcdef0
+// ASM:       - 0xfedcba9876543210
+// ASM:     .registers:      
+// ASM:       0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0
+// ASM:       0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000
+// ASM:       0xa1b3 (SPI_PS_INPUT_ENA): 0x1
+// ASM:       0xa1b4 (SPI_PS_INPUT_ADDR): 0x1
+// ASM: ...
+// ASM: 	.end_amdgpu_pal_metadata
+
+// ELF: SHT_NOTE
+// ELF:       0000: 07000000 BD000000 20000000 414D4447  |........ ...AMDG|
+// ELF:       0010: 50550000 81B0616D 6470616C 2E706970  |PU....amdpal.pip|
+// ELF:       0020: 656C696E 65739183 B02E6861 72647761  |elines....hardwa|
+// ELF:       0030: 72655F73 74616765 7381A32E 707384AC  |re_stages...ps..|
+// ELF:       0040: 2E656E74 72795F70 6F696E74 A970735F  |.entry_point.ps_|
+// ELF:       0050: 616D6470 616CB42E 73637261 7463685F  |amdpal..scratch_|
+// ELF:       0060: 6D656D6F 72795F73 697A6500 AB2E7367  |memory_size...sg|
+// ELF:       0070: 70725F63 6F756E74 01AB2E76 6770725F  |pr_count...vgpr_|
+// ELF:       0080: 636F756E 7401B72E 696E7465 726E616C  |count...internal|
+// ELF:       0090: 5F706970 656C696E 655F6861 736892CF  |_pipeline_hash..|
+// ELF:       00A0: 12345678 9ABCDEF0 CFFEDCBA 98765432  |.4Vx.........vT2|
+// ELF:       00B0: 10AA2E72 65676973 74657273 84CD2C0A  |...registers..,.|
+// ELF:       00C0: 00CD2C0B CE420000 00CDA1B3 01CDA1B4  |..,..B..........|
+// ELF:       00D0: 01000000                             |....|
+
+