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authorAkira Hatanaka <ahatanaka@apple.com>2017-04-20 22:47:56 +0000
committerAkira Hatanaka <ahatanaka@apple.com>2017-04-20 22:47:56 +0000
commite327f098329f0dd1bd7f7dc0a29c111cf08eb9cd (patch)
tree786c55da20d1b9ea588dc1f5dd9e5a7feaf21dd7 /llvm/test
parentcc663b82fa6ec3c77d2cba38c9a86e611d0c4a74 (diff)
downloadbcm5719-llvm-e327f098329f0dd1bd7f7dc0a29c111cf08eb9cd.tar.gz
bcm5719-llvm-e327f098329f0dd1bd7f7dc0a29c111cf08eb9cd.zip
[AArch64] Improve code generation for logical instructions taking
immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 300913
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/AArch64/optimize-imm.ll64
1 files changed, 64 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/optimize-imm.ll b/llvm/test/CodeGen/AArch64/optimize-imm.ll
new file mode 100644
index 00000000000..a4725c65aa2
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/optimize-imm.ll
@@ -0,0 +1,64 @@
+; RUN: llc -o - %s -mtriple=aarch64-- | FileCheck %s
+
+; CHECK-LABEL: and1:
+; CHECK: and {{w[0-9]+}}, w0, #0xfffffffd
+
+define void @and1(i32 %a, i8* nocapture %p) {
+entry:
+ %and = and i32 %a, 253
+ %conv = trunc i32 %and to i8
+ store i8 %conv, i8* %p, align 1
+ ret void
+}
+
+; (a & 0x3dfd) | 0xffffc000
+;
+; CHECK-LABEL: and2:
+; CHECK: and {{w[0-9]+}}, w0, #0xfdfdfdfd
+
+define i32 @and2(i32 %a) {
+entry:
+ %and = and i32 %a, 15869
+ %or = or i32 %and, -16384
+ ret i32 %or
+}
+
+; (a & 0x19) | 0xffffffc0
+;
+; CHECK-LABEL: and3:
+; CHECK: and {{w[0-9]+}}, w0, #0x99999999
+
+define i32 @and3(i32 %a) {
+entry:
+ %and = and i32 %a, 25
+ %or = or i32 %and, -64
+ ret i32 %or
+}
+
+; (a & 0xc5600) | 0xfff1f1ff
+;
+; CHECK-LABEL: and4:
+; CHECK: and {{w[0-9]+}}, w0, #0xfffc07ff
+
+define i32 @and4(i32 %a) {
+entry:
+ %and = and i32 %a, 787968
+ %or = or i32 %and, -921089
+ ret i32 %or
+}
+
+; Make sure we don't shrink or optimize an XOR's immediate operand if the
+; immediate is -1. Instruction selection turns (and ((xor $mask, -1), $v0)) into
+; a BIC.
+
+; CHECK-LABEL: xor1:
+; CHECK: orr [[R0:w[0-9]+]], wzr, #0x38
+; CHECK: bic {{w[0-9]+}}, [[R0]], w0, lsl #3
+
+define i32 @xor1(i32 %a) {
+entry:
+ %shl = shl i32 %a, 3
+ %xor = and i32 %shl, 56
+ %and = xor i32 %xor, 56
+ ret i32 %and
+}
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