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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-05-11 09:28:27 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-05-11 09:28:27 +0000 |
| commit | ddc67a76559e699ead5aa5f82cecfdebec75a8be (patch) | |
| tree | 2c0e00d96041c6acc95cb2993be718bb71f24cde /llvm/test | |
| parent | 5a719f9b9a4142f0d97894f37f084555146bb3d2 (diff) | |
| download | bcm5719-llvm-ddc67a76559e699ead5aa5f82cecfdebec75a8be.tar.gz bcm5719-llvm-ddc67a76559e699ead5aa5f82cecfdebec75a8be.zip | |
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
llvm-svn: 156609
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt | 62 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt | 5 |
2 files changed, 67 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt b/llvm/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt new file mode 100644 index 00000000000..6f1da8eb237 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt @@ -0,0 +1,62 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s -check-prefix=CHECK-WARN +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x03 0xaf 0x06 +# CHECK: sxtb +0x74 0x03 0xaf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xbf 0x06 +# CHECK: sxth +0x74 0x3f 0xbf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xa6 0x06 +# CHECK: sxtab +0x74 0x3f 0xa6 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xb7 0x06 +# CHECK: sxtah +0x74 0x3f 0xb7 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0x8f 0x06 +# CHECK: sxtb16 +0x74 0x3f 0x8f 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0x86 0x06 +# CHECK: sxtab16 +0x74 0x3f 0x86 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xef 0x06 +# CHECK: uxtb +0x74 0x3f 0xef 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xff 0x06 +# CHECK: uxth +0x74 0x3f 0xff 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xcf 0x06 +# CHECK: uxtb16 +0x74 0x3f 0xcf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xe4 0x06 +# CHECK: uxtab +0x74 0x3f 0xe4 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xf2 0x06 +# CHECK: uxtah +0x74 0x3f 0xf2 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xc4 0x06 +# CHECK: uxtab16 +0x74 0x3f 0xc4 0x06 diff --git a/llvm/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt b/llvm/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt new file mode 100644 index 00000000000..d7939c19180 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xb4 0x38 0x80 0x06 +0xb4 0x38 0x80 0x06 |
