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authorJim Grosbach <grosbach@apple.com>2012-03-30 18:53:01 +0000
committerJim Grosbach <grosbach@apple.com>2012-03-30 18:53:01 +0000
commitdaa04130ed75e5c42a99bac91ac22306f9af8987 (patch)
tree29e43c565b4dbf8e3595d4f5c926d475253add5a /llvm/test
parent74005ae691e7e362c175be695fe46e5d4e760005 (diff)
downloadbcm5719-llvm-daa04130ed75e5c42a99bac91ac22306f9af8987.tar.gz
bcm5719-llvm-daa04130ed75e5c42a99bac91ac22306f9af8987.zip
ARM encoding for VSWP got the second operand incorrect.
Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 llvm-svn: 153766
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/MC/ARM/neon-vswp.s7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/test/MC/ARM/neon-vswp.s b/llvm/test/MC/ARM/neon-vswp.s
new file mode 100644
index 00000000000..2138eedf4c2
--- /dev/null
+++ b/llvm/test/MC/ARM/neon-vswp.s
@@ -0,0 +1,7 @@
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
+
+vswp d1, d2
+vswp q1, q2
+
+@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]
+@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]
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