[mips] MIPSR6 Compact jump support

This patch adds support for compact jumps similiar to the previous compact
branch support for MIPSR6. Unlike compact branches, compact jumps do not
have a forbidden slot.

As MipsInstrInfo::getEquivalentCompactForm can determine the correct
expansion for jumps and branches for both microMIPS and MIPSR6, remove the
unnecessary distinction in the delay slot filler.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders
llvm-svn: 265390

6 files changed, 154 insertions, 75 deletions

diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll b/llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll
index e863c740943..b489a23f69e 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll
@@ -1,21 +1,26 @@
-; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32
+; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC
 
 ; Function Attrs: nounwind
 define void @l()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
+; PIC: jialc $25, 0
   %call1 = tail call i32 @j()
   %cmp = icmp eq i32 %call, %call1
 ; CHECK: bnec
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext -2)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
@@ -28,19 +33,23 @@ declare void @f(i32 signext)
 ; Function Attrs: define void @l2()  {
 define void @l2()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
+; PIC: jialc $25, 0
   %call1 = tail call i32 @i()
   %cmp = icmp eq i32 %call, %call1
 ; CHECK beqc
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext -1)
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
+; CHECK: jic $ra, 0
   ret void
 }
 
@@ -49,18 +58,21 @@ declare i32 @i()
 ; Function Attrs: nounwind
 define void @l3()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
   %cmp = icmp slt i32 %call, 0
 ; CHECK : bgez
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 0)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
@@ -73,83 +85,122 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
   tail call void @f(i32 signext 1)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l5()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
+; PIC: jialc $25, 0
   %cmp = icmp sgt i32 %call, 0
 ; CHECK: blezc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 2) 
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l6()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
+; PIC: jialc $25, 0
   %cmp = icmp sgt i32 %call, -1
 ; CHECK: bltzc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 3)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l7()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
   %cmp = icmp eq i32 %call, 0
 ; CHECK: bnezc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 4)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l8()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
   %cmp = icmp eq i32 %call, 0
 ; CHECK: beqzc
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 5)
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
+; CHECK: jic $ra, 0
   ret void
 }
+
+define i32 @l9(i8* ()* %i) #0 {
+entry:
+  %i.addr = alloca i8* ()*, align 4
+  store i8* ()* %i, i8* ()** %i.addr, align 4
+; STATIC32: jal
+; STATIC32: nop
+; PIC: jialc $25, 0
+  %call = call i32 @k()
+; PIC: jialc $25, 0
+  %cmp = icmp ne i32 %call, 0
+; CHECK: beqzc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %0 = load i8* ()*, i8* ()** %i.addr, align 4
+; CHECK: jialc $25, 0
+  %call1 = call i8* %0()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
+  ret i32 -1
+}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/call.ll b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
index a4b03405f72..9b46d3b0960 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/call.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
@@ -1,18 +1,18 @@
 ; Test the 'call' instruction and the tailcall variant.
 
 ; FIXME: We should remove the need for -enable-mips-tail-calls
-; RUN: llc -march=mips   -mcpu=mips32   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips64 -mcpu=mips4    -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
+; RUN: llc -march=mips   -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
+; RUN: llc -march=mips   -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
+; RUN: llc -march=mips64 -mcpu=mips4    -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C
 
 declare void @extern_void_void()
 declare i32 @extern_i32_void()
@@ -25,7 +25,8 @@ define i32 @call_void_void() {
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
-; ALL:           jalr $[[TGT]]
+; NOT-R6C:       jalr $[[TGT]]
+; R6C:           jialc $[[TGT]], 0
 
   call void @extern_void_void()
   ret i32 0
@@ -38,7 +39,8 @@ define i32 @call_i32_void() {
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
-; ALL:           jalr $[[TGT]]
+; NOT-R6C:       jalr $[[TGT]]
+; R6C:           jialc $[[TGT]], 0
 
   %1 = call i32 @extern_i32_void()
   %2 = add i32 %1, 1
@@ -55,9 +57,9 @@ define float @call_float_void() {
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
 
-; ALL:           jalr $[[TGT]]
+; NOT-R6C:       jalr $[[TGT]]
+; R6C:           jialc $[[TGT]], 0
 
-; O32:           move $gp, $[[GP]]
 
   %1 = call float @extern_float_void()
   %2 = fadd float %1, 1.0
@@ -71,8 +73,7 @@ define void @musttail_call_void_void() {
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
-; NOT-R6:        jr $[[TGT]]
-; R6:            r6.jr $[[TGT]]
+; ALL:           jr $[[TGT]]
 
   musttail call void @extern_void_void()
   ret void
@@ -85,8 +86,7 @@ define i32 @musttail_call_i32_void() {
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
-; NOT-R6:        jr $[[TGT]]
-; R6:            r6.jr $[[TGT]]
+; ALL:           jr $[[TGT]]
 
   %1 = musttail call i32 @extern_i32_void()
   ret i32 %1
@@ -99,8 +99,7 @@ define float @musttail_call_float_void() {
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
 
-; NOT-R6:        jr $[[TGT]]
-; R6:            r6.jr $[[TGT]]
+; ALL:           jr $[[TGT]]
 
   %1 = musttail call float @extern_float_void()
   ret float %1
@@ -110,7 +109,9 @@ define i32 @indirect_call_void_void(void ()* %addr) {
 ; ALL-LABEL: indirect_call_void_void:
 
 ; ALL:           move $25, $4
-; ALL:           jalr $25
+; NOT-R6C:       jalr $25
+; R6C:           jialc $25, 0
+
 
   call void %addr()
   ret i32 0
@@ -120,7 +121,9 @@ define i32 @indirect_call_i32_void(i32 ()* %addr) {
 ; ALL-LABEL: indirect_call_i32_void:
 
 ; ALL:           move $25, $4
-; ALL:           jalr $25
+; NOT-R6C:       jalr $25
+; R6C:           jialc $25, 0
+
 
   %1 = call i32 %addr()
   %2 = add i32 %1, 1
@@ -131,7 +134,9 @@ define float @indirect_call_float_void(float ()* %addr) {
 ; ALL-LABEL: indirect_call_float_void:
 
 ; ALL:           move $25, $4
-; ALL:           jalr $25
+; NOT-R6C:       jalr $25
+; R6C:           jialc $25, 0
+
 
   %1 = call float %addr()
   %2 = fadd float %1, 1.0
@@ -178,7 +183,8 @@ define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr a
 ; ALL-LABEL: thunk_undef_double:
 ; O32: # implicit-def: %A2
 ; O32: # implicit-def: %A3
-; ALL: jr $25
+; ALL:        jr $25
+
   tail call void @undef_double(i32 undef, double undef) #8
   ret void
 }
@@ -190,7 +196,8 @@ define i32 @jal_only_allows_symbols() {
 ; ALL-NOT:       {{jal }}
 ; ALL:           addiu $[[TGT:[0-9]+]], $zero, 1234
 ; ALL-NOT:       {{jal }}
-; ALL:           jalr $[[TGT]]
+; NOT-R6C:       jalr $[[TGT]]
+; R6C:           jialc $[[TGT]], 0
 ; ALL-NOT:       {{jal }}
 
   call void () inttoptr (i32 1234 to void ()*)()
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
index debfeb35b21..4fdce5a0490 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
@@ -4,7 +4,7 @@
 ; RUN: llc -march=mips   -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
-; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
+; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6C
 ; RUN: llc -march=mips64 -mcpu=mips4    -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
@@ -15,16 +15,19 @@
 define i32 @br(i8 *%addr) {
 ; ALL-LABEL: br:
 ; NOT-R6:        jr $4 # <MCInst #{{[0-9]+}} JR
-; R6:            jr $4 # <MCInst #{{[0-9]+}} JALR
+; R6C:           jic $4, 0 # <MCInst #{{[0-9]+}} JIC
+
 
 ; ALL: $BB0_1: # %L1
 ; NOT-R6:        jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6:            jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C:           jr $ra # <MCInst #{{[0-9]+}} JALR
 ; ALL:           addiu $2, $zero, 0
 
 ; ALL: $BB0_2: # %L2
 ; NOT-R6:        jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6:            jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C:           jr $ra # <MCInst #{{[0-9]+}} JALR
 ; ALL:           addiu $2, $zero, 1
 
 entry:
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
index 0561c24219c..de104f97551 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
@@ -11,19 +11,27 @@
 ; RUN: llc -march=mips   -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
+; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6C
 ; RUN: llc -march=mips64 -mcpu=mips4    -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
+
+; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled
+;        as mthc1 has unmodeled side effects. This is an artifact of our backend.
+;        Force the delay slot filler off to check that the sequence jr $ra; nop is
+;        turned into jic 0, $ra.
+
+; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 \
+; RUN:     -check-prefix=R6C
 
 define void @ret_void() {
 ; ALL-LABEL: ret_void:
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
 
   ret void
 }
@@ -173,6 +181,7 @@ define float @ret_float_0x3() {
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
 
 ; float constants are written as double constants
   ret float 0x36b8000000000000
@@ -191,6 +200,7 @@ define double @ret_double_0x0() {
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
 
   ret double 0x0000000000000000
 }
@@ -204,6 +214,7 @@ define double @ret_double_0x3() {
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
 
   ret double 0x0000000000000003
 }
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index d9c93810438..66a2f95cde2 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -1,11 +1,11 @@
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips4 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT -check-prefix=PRER6
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT -check-prefix=PRER6
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT -check-prefix=PRER6
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=CMP_CC_FMT
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=CMP_CC_FMT -check-prefix=R6
 
 @gld0 = external global fp128
 @gld1 = external global fp128
@@ -544,10 +544,11 @@ entry:
 }
 
 ; ALL-LABEL: load_LD_float:
-; ALL: ld   $[[R0:[0-9]+]], %got_disp(gf1)
-; ALL: lw   $4, 0($[[R0]])
-; ALL: ld   $25, %call16(__extendsftf2)
-; ALL: jalr $25
+; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gf1)
+; ALL:   lw   $4, 0($[[R0]])
+; ALL:   ld   $25, %call16(__extendsftf2)
+; PRER6: jalr $25
+; R6:    jialc $25, 0
 
 define fp128 @load_LD_float() {
 entry:
@@ -557,10 +558,11 @@ entry:
 }
 
 ; ALL-LABEL: load_LD_double:
-; ALL: ld   $[[R0:[0-9]+]], %got_disp(gd1)
-; ALL: ld   $4, 0($[[R0]])
-; ALL: ld   $25, %call16(__extenddftf2)
-; ALL: jalr $25
+; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gd1)
+; ALL:   ld   $4, 0($[[R0]])
+; ALL:   ld   $25, %call16(__extenddftf2)
+; PRER6: jalr $25
+; R6:    jialc $25, 0
 
 define fp128 @load_LD_double() {
 entry:
@@ -585,13 +587,14 @@ entry:
 }
 
 ; ALL-LABEL: store_LD_float:
-; ALL: ld   $[[R0:[0-9]+]], %got_disp(gld1)
-; ALL: ld   $4, 0($[[R0]])
-; ALL: ld   $5, 8($[[R0]])
-; ALL: ld   $25, %call16(__trunctfsf2)
-; ALL: jalr $25
-; ALL: ld   $[[R1:[0-9]+]], %got_disp(gf1)
-; ALL: sw   $2, 0($[[R1]])
+; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gld1)
+; ALL:   ld   $4, 0($[[R0]])
+; ALL:   ld   $5, 8($[[R0]])
+; ALL:   ld   $25, %call16(__trunctfsf2)
+; PRER6: jalr $25
+; R6:    jialc $25, 0
+; ALL:   ld   $[[R1:[0-9]+]], %got_disp(gf1)
+; ALL:   sw   $2, 0($[[R1]])
 
 define void @store_LD_float() {
 entry:
@@ -602,13 +605,14 @@ entry:
 }
 
 ; ALL-LABEL: store_LD_double:
-; ALL: ld   $[[R0:[0-9]+]], %got_disp(gld1)
-; ALL: ld   $4, 0($[[R0]])
-; ALL: ld   $5, 8($[[R0]])
-; ALL: ld   $25, %call16(__trunctfdf2)
-; ALL: jalr $25
-; ALL: ld   $[[R1:[0-9]+]], %got_disp(gd1)
-; ALL: sd   $2, 0($[[R1]])
+; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gld1)
+; ALL:   ld   $4, 0($[[R0]])
+; ALL:   ld   $5, 8($[[R0]])
+; ALL:   ld   $25, %call16(__trunctfdf2)
+; PRER6: jalr $25
+; R6:    jialc $25, 0
+; ALL:   ld   $[[R1:[0-9]+]], %got_disp(gd1)
+; ALL:   sd   $2, 0($[[R1]])
 
 define void @store_LD_double() {
 entry:
@@ -648,7 +652,8 @@ entry:
 ; ALL:           move $[[R2:[0-9]+]], $9
 ; ALL:           move $[[R3:[0-9]+]], $8
 ; ALL:           ld   $25, %call16(__gttf2)($gp)
-; ALL:           jalr $25
+; PRER6:         jalr $25
+; R6:            jialc $25, 0
 
 ; C_CC_FMT:      slti $[[CC:[0-9]+]], $2, 1
 ; C_CC_FMT:      movz $[[R1]], $[[R3]], $[[CC]]
diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s
index 0cc8d4d91a3..8e759a0ee6b 100644
--- a/llvm/test/MC/Mips/mips32r6/valid.s
+++ b/llvm/test/MC/Mips/mips32r6/valid.s
@@ -165,6 +165,8 @@ a:
         jr      $25              # CHECK: jr $25                 # encoding: [0x03,0x20,0x00,0x09]
         jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
+        jialc   $15, 16161       # CHECK: jialc $15, 16161       # encoding: [0xf8,0x0f,0x3f,0x21]
+        jic     $12, -3920       # CHECK: jic $12, -3920         # encoding: [0xd8,0x0c,0xf0,0xb0]
         ldc2    $8, -701($at)    # CHECK: ldc2 $8, -701($1)      # encoding: [0x49,0xc8,0x0d,0x43]
         lwc2    $18,-841($a2)    # CHECK: lwc2 $18, -841($6)     # encoding: [0x49,0x52,0x34,0xb7]
         sdc2    $20,629($s2)     # CHECK: sdc2 $20, 629($18)     # encoding: [0x49,0xf4,0x92,0x75]