[globalisel][tablegen] Added instruction emission to the state-machine-based matcher.

Summary:
This further improves the compile-time regressions that will be caused by a
re-commit of r303259.

Also added included preliminary work in preparation for the multi-insn emitter
since I needed to change the relevant part of the API for this patch anyway.

Depends on D33758

Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar

Reviewed By: ab

Subscribers: kristof.beyls, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D33764

llvm-svn: 307133

1 files changed, 221 insertions, 155 deletions

diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td
index 599cf863fdc..f959dd8c0ac 100644
--- a/llvm/test/TableGen/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter.td
@@ -107,19 +107,23 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable0\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable0, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // (select:i32 GPR32:i32:$src1, complex:i32:$src2, complex:i32:$src3) => (INSN2:i32 GPR32:i32:$src1, complex:i32:$src3, complex:i32:$src2)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::INSN2));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(1)/*src1*/);
-// CHECK-NEXT:    Renderers[1](MIB);
-// CHECK-NEXT:    Renderers[0](MIB);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable0[] = {
+// CHECK-NEXT:      // (select:i32 GPR32:i32:$src1, complex:i32:$src2, complex:i32:$src3) => (INSN2:i32 GPR32:i32:$src1, complex:i32:$src3, complex:i32:$src2)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN2,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/1,
+// CHECK-NEXT:      GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable0\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable0, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -146,11 +150,17 @@ def : Pat<(select GPR32:$src1, complex:$src2, complex:$src3),
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable1\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable1, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // (add:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (ADD:i32 GPR32:i32:$src1, GPR32:i32:$src2)
-// CHECK-NEXT:    I.setDesc(TII.get(MyTarget::ADD));
-// CHECK-NEXT:    MachineInstr &NewI = I;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable1[] = {
+// CHECK-NEXT:      // (add:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (ADD:i32 GPR32:i32:$src1, GPR32:i32:$src2)
+// CHECK-NEXT:      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/ 0, /*Opcode*/MyTarget::ADD,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable1\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable1, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -186,21 +196,25 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable2\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable2, MRI, TRI, RBI, AvailableFeatures)) {
 // CHECK-NEXT:    if (!isObviouslySafeToFold(*State.MIs[1]))
 // CHECK-NEXT:      return false;
-// CHECK-NEXT:    // (mul:i32 (add:i32 GPR32:i32:$src1, GPR32:i32:$src2), GPR32:i32:$src3)  =>  (MULADD:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MULADD));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    MIB.add(State.MIs[1]->getOperand(1)/*src1*/);
-// CHECK-NEXT:    MIB.add(State.MIs[1]->getOperand(2)/*src2*/);
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(2)/*src3*/);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], State.MIs[1], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable2[] = {
+// CHECK-NEXT:      // (mul:i32 (add:i32 GPR32:i32:$src1, GPR32:i32:$src2), GPR32:i32:$src3)  =>  (MULADD:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable2\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable2, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -232,23 +246,27 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable3\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable3, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:     if (!isObviouslySafeToFold(*State.MIs[1]))
-// CHECK-NEXT:       return false;
-// CHECK-NEXT:     // (mul:i32 GPR32:i32:$src3, (add:i32 GPR32:i32:$src1, GPR32:i32:$src2))  =>  (MULADD:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3)
-// CHECK-NEXT:     MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MULADD));
-// CHECK-NEXT:     MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:     MIB.add(State.MIs[1]->getOperand(1)/*src1*/);
-// CHECK-NEXT:     MIB.add(State.MIs[1]->getOperand(2)/*src2*/);
-// CHECK-NEXT:     MIB.add(State.MIs[0]->getOperand(1)/*src3*/);
-// CHECK-NEXT:     for (const auto *FromMI : {State.MIs[0], State.MIs[1], })
-// CHECK-NEXT:       for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:         MIB.addMemOperand(MMO);
-// CHECK-NEXT:     I.eraseFromParent();
-// CHECK-NEXT:     MachineInstr &NewI = *MIB;
-// CHECK-NEXT:     constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
-// CHECK-NEXT:     return true;
-// CHECK-NEXT:   }
+// CHECK-NEXT:    if (!isObviouslySafeToFold(*State.MIs[1]))
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    const static int64_t EmitTable3[] = {
+// CHECK-NEXT:      // (mul:i32 GPR32:i32:$src3, (add:i32 GPR32:i32:$src1, GPR32:i32:$src2))  =>  (MULADD:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable3\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable3, TII, TRI, RBI);
+// CHECK-NEXT:    return true;
+// CHECK-NEXT:  }
 
 def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
                [(set GPR32:$dst,
@@ -274,18 +292,22 @@ def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable4\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable4, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:   // (mul:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (MUL:i32 GPR32:i32:$src2, GPR32:i32:$src1)
-// CHECK-NEXT:   MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MUL));
-// CHECK-NEXT:   MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:   MIB.add(State.MIs[0]->getOperand(2)/*src2*/);
-// CHECK-NEXT:   MIB.add(State.MIs[0]->getOperand(1)/*src1*/);
-// CHECK-NEXT:   for (const auto *FromMI : {State.MIs[0], })
-// CHECK-NEXT:     for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:       MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable4[] = {
+// CHECK-NEXT:      // (mul:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (MUL:i32 GPR32:i32:$src2, GPR32:i32:$src1)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable4\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable4, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -332,24 +354,28 @@ def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable5\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable5, MRI, TRI, RBI, AvailableFeatures)) {
 // CHECK-NEXT:    if (!isObviouslySafeToFold(*State.MIs[1]))
 // CHECK-NEXT:      return false;
 // CHECK-NEXT:    if (!isObviouslySafeToFold(*State.MIs[2]))
 // CHECK-NEXT:      return false;
-// CHECK-NEXT:    // (sub:i32 (sub:i32 GPR32:i32:$src1, GPR32:i32:$src2), (sub:i32 GPR32:i32:$src3, GPR32:i32:$src4)) => (INSNBOB:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3, GPR32:i32:$src4)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::INSNBOB));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    MIB.add(State.MIs[1]->getOperand(1)/*src1*/);
-// CHECK-NEXT:    MIB.add(State.MIs[1]->getOperand(2)/*src2*/);
-// CHECK-NEXT:    MIB.add(State.MIs[2]->getOperand(1)/*src3*/);
-// CHECK-NEXT:    MIB.add(State.MIs[2]->getOperand(2)/*src4*/);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], State.MIs[1], State.MIs[2], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable5[] = {
+// CHECK-NEXT:      // (sub:i32 (sub:i32 GPR32:i32:$src1, GPR32:i32:$src2), (sub:i32 GPR32:i32:$src3, GPR32:i32:$src4)) => (INSNBOB:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3, GPR32:i32:$src4)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSNBOB,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src3
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src4
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable5\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable5, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -377,18 +403,22 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable6\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable6, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // (sub:i32 GPR32:i32:$src1, complex:i32:$src2) => (INSN1:i32 GPR32:i32:$src1, complex:i32:$src2)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::INSN1));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(1)/*src1*/);
-// CHECK-NEXT:    Renderers[0](MIB);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable6[] = {
+// CHECK-NEXT:      // (sub:i32 GPR32:i32:$src1, complex:i32:$src2) => (INSN1:i32 GPR32:i32:$src1, complex:i32:$src2)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN1,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable6\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable6, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -414,18 +444,22 @@ def : Pat<(sub GPR32:$src1, complex:$src2), (INSN1 GPR32:$src1, complex:$src2)>;
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable7\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable7, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // (xor:i32 GPR32:i32:$src1, -2:i32) => (XORI:i32 GPR32:i32:$src1)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XORI));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    MIB.addImm(-1);
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(1)/*src1*/);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable7[] = {
+// CHECK-NEXT:      // (xor:i32 GPR32:i32:$src1, -2:i32) => (XORI:i32 GPR32:i32:$src1)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORI,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable7\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable7, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -452,18 +486,22 @@ def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1),
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable8\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable8, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // (xor:i32 GPR32:i32:$src1, -3:i32) => (XOR:i32 GPR32:i32:$src1)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XOR));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    MIB.addReg(MyTarget::R0);
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(1)/*src1*/);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable8[] = {
+// CHECK-NEXT:      // (xor:i32 GPR32:i32:$src1, -3:i32) => (XOR:i32 GPR32:i32:$src1)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XOR,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable8\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable8, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -490,19 +528,23 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1),
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable9\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable9, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // (xor:i32 GPR32:i32:$src1, -4:i32) => (XORlike:i32 GPR32:i32:$src1)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XORlike));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    MIB.addImm(-1);
-// CHECK-NEXT:    MIB.addReg(MyTarget::R0);
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(1)/*src1*/);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable9[] = {
+// CHECK-NEXT:      // (xor:i32 GPR32:i32:$src1, -4:i32) => (XORlike:i32 GPR32:i32:$src1)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORlike,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
+// CHECK-NEXT:      GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable9\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable9, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -529,20 +571,24 @@ def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1),
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable10\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable10, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // (xor:i32 GPR32:i32:$src1, -5:i32) => (XORManyDefaults:i32 GPR32:i32:$src1)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XORManyDefaults));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    MIB.addImm(-1);
-// CHECK-NEXT:    MIB.addReg(MyTarget::R0);
-// CHECK-NEXT:    MIB.addReg(MyTarget::R0);
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(1)/*src1*/);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable10[] = {
+// CHECK-NEXT:      // (xor:i32 GPR32:i32:$src1, -5:i32) => (XORManyDefaults:i32 GPR32:i32:$src1)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORManyDefaults,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
+// CHECK-NEXT:      GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
+// CHECK-NEXT:      GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable10\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable10, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -571,18 +617,22 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1)
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable11\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable11, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // (xor:i32 GPR32:i32:$Wm, -1:i32) => (ORN:i32 R0:i32, GPR32:i32:$Wm)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::ORN));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    MIB.addReg(MyTarget::R0);
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(1)/*Wm*/);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable11[] = {
+// CHECK-NEXT:      // (xor:i32 GPR32:i32:$Wm, -1:i32) => (ORN:i32 R0:i32, GPR32:i32:$Wm)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ORN,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable11\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable11, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -605,11 +655,17 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable12\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable12, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // (bitconvert:i32 FPR32:f32:$src1) => (COPY_TO_REGCLASS:i32 FPR32:f32:$src1, GPR32:i32)
-// CHECK-NEXT:    I.setDesc(TII.get(TargetOpcode::COPY));
-// CHECK-NEXT:    MachineInstr &NewI = I;
-// CHECK-NEXT:    constrainOperandRegToRegClass(NewI, 0, MyTarget::GPR32RegClass, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable12[] = {
+// CHECK-NEXT:      // (bitconvert:i32 FPR32:f32:$src1) => (COPY_TO_REGCLASS:i32 FPR32:f32:$src1, GPR32:i32)
+// CHECK-NEXT:      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/ 0, /*Opcode*/TargetOpcode::COPY,
+// CHECK-NEXT:      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/ 1,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable12\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable12, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -630,16 +686,20 @@ def : Pat<(i32 (bitconvert FPR32:$src1)),
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable13\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable13, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:    // 1:i32 => (MOV1:i32)
-// CHECK-NEXT:    MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MOV1));
-// CHECK-NEXT:    MIB.add(State.MIs[0]->getOperand(0)/*dst*/);
-// CHECK-NEXT:    for (const auto *FromMI : {State.MIs[0], })
-// CHECK-NEXT:      for (const auto &MMO : FromMI->memoperands())
-// CHECK-NEXT:        MIB.addMemOperand(MMO);
-// CHECK-NEXT:    I.eraseFromParent();
-// CHECK-NEXT:    MachineInstr &NewI = *MIB;
-// CHECK-NEXT:    constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:    const static int64_t EmitTable13[] = {
+// CHECK-NEXT:      // 1:i32  =>  (MOV1:i32)
+// CHECK-NEXT:      GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV1,
+// CHECK-NEXT:      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:      GIR_MergeMemOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable13\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable13, TII, TRI, RBI);
 // CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
@@ -656,12 +716,18 @@ def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>;
 // CHECK-NEXT:  };
 // CHECK-NEXT:  MIs.clear();
 // CHECK-NEXT:  MIs.push_back(&I);
+// CHECK-NEXT:  DEBUG(dbgs() << "Processing MatchTable14\n");
 // CHECK-NEXT:  if (executeMatchTable(*this, State, MatcherInfo, MatchTable14, MRI, TRI, RBI, AvailableFeatures)) {
-// CHECK-NEXT:     // (br (bb:Other):$target) => (BR (bb:Other):$target)
-// CHECK-NEXT:     I.setDesc(TII.get(MyTarget::BR));
-// CHECK-NEXT:     MachineInstr &NewI = I;
-// CHECK-NEXT:     constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
-// CHECK-NEXT:     return true;
+// CHECK-NEXT:    const static int64_t EmitTable14[] = {
+// CHECK-NEXT:      // (br (bb:Other):$target) => (BR (bb:Other):$target)
+// CHECK-NEXT:      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/ 0, /*Opcode*/MyTarget::BR,
+// CHECK-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:      GIR_Done,
+// CHECK-NEXT:    };
+// CHECK-NEXT:    NewMIVector OutMIs;
+// CHECK-NEXT:    DEBUG(dbgs() << "Processing EmitTable14\n");
+// CHECK-NEXT:    executeEmitTable(OutMIs, State, EmitTable14, TII, TRI, RBI);
+// CHECK-NEXT:    return true;
 // CHECK-NEXT:  }
 
 def BR : I<(outs), (ins unknown:$target),