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| author | Mihai Popa <mihail.popa@gmail.com> | 2013-07-03 09:21:44 +0000 |
|---|---|---|
| committer | Mihai Popa <mihail.popa@gmail.com> | 2013-07-03 09:21:44 +0000 |
| commit | d36cbaa4231e51a42d761d298ff20aaa6e88d014 (patch) | |
| tree | 978fd1c7d3586a4133e477ce7e8d4ead7357e2ad /llvm/test | |
| parent | 36b2417f18f4b44d184cb54b5395d2f3e4397b18 (diff) | |
| download | bcm5719-llvm-d36cbaa4231e51a42d761d298ff20aaa6e88d014.tar.gz bcm5719-llvm-d36cbaa4231e51a42d761d298ff20aaa6e88d014.zip | |
This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits
llvm-svn: 185528
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/ARM/basic-thumb-instructions.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/basic-thumb2-instructions.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/thumb1.txt | 6 |
3 files changed, 16 insertions, 6 deletions
diff --git a/llvm/test/MC/ARM/basic-thumb-instructions.s b/llvm/test/MC/ARM/basic-thumb-instructions.s index 22e21da88e4..b48db9a4d8e 100644 --- a/llvm/test/MC/ARM/basic-thumb-instructions.s +++ b/llvm/test/MC/ARM/basic-thumb-instructions.s @@ -85,11 +85,15 @@ _func: @ ADR @------------------------------------------------------------------------------ adr r2, _baz - adr r2, #3 + adr r5, #0 + adr r2, #4 + adr r3, #1020 @ CHECK: adr r2, _baz @ encoding: [A,0xa2] @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10 -@ CHECK: adr r2, #3 @ encoding: [0x03,0xa2] +@ CHECK: adr r5, #0 @ encoding: [0x00,0xa5] +@ CHECK: adr r2, #4 @ encoding: [0x01,0xa2] +@ CHECK: adr r3, #1020 @ encoding: [0xff,0xa3] @------------------------------------------------------------------------------ @ ASR (immediate) diff --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s index b529a26ade8..c331d5d522b 100644 --- a/llvm/test/MC/ARM/basic-thumb2-instructions.s +++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s @@ -134,12 +134,14 @@ _func: @------------------------------------------------------------------------------ subw r11, pc, #3270 + adr.w r2, #3 adr.w r11, #-826 adr.w r1, #-0x0 -@ CHECK: subw r11, pc, #3270 @ encoding: [0xaf,0xf6,0xc6,0x4b] -@ CHECK: adr.w r11, #-826 @ encoding: [0xaf,0xf2,0x3a,0x3b] -@ CHECK: adr.w r1, #-0 @ encoding: [0xaf,0xf2,0x00,0x01] +@ CHECK: subw r11, pc, #3270 @ encoding: [0xaf,0xf6,0xc6,0x4b] +@ CHECK: adr.w r2, #3 @ encoding: [0x0f,0xf2,0x03,0x02] +@ CHECK: adr.w r11, #-826 @ encoding: [0xaf,0xf2,0x3a,0x3b] +@ CHECK: adr.w r1, #-0 @ encoding: [0xaf,0xf2,0x00,0x01] @------------------------------------------------------------------------------ @ AND (immediate) diff --git a/llvm/test/MC/Disassembler/ARM/thumb1.txt b/llvm/test/MC/Disassembler/ARM/thumb1.txt index 7362d9b9b2d..a129abba70f 100644 --- a/llvm/test/MC/Disassembler/ARM/thumb1.txt +++ b/llvm/test/MC/Disassembler/ARM/thumb1.txt @@ -54,8 +54,12 @@ #------------------------------------------------------------------------------ # ADR #------------------------------------------------------------------------------ -# CHECK: adr r2, #3 +# CHECK: adr r5, #0 +# CHECK: adr r2, #12 +# CHECK: adr r3, #1020 +0x00 0xa5 0x03 0xa2 +0xff 0xa3 #------------------------------------------------------------------------------ # ASR (immediate) |
