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authorEvan Cheng <evan.cheng@apple.com>2010-03-05 03:08:23 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-03-05 03:08:23 +0000
commitcf67ffa50027baab4e8c838a73bddde215450807 (patch)
tree432ce3c70207c80620bf32fd309ce2120af7d28d /llvm/test
parent998c7c2614c306128c59a1f304c2a42b25933fff (diff)
downloadbcm5719-llvm-cf67ffa50027baab4e8c838a73bddde215450807.tar.gz
bcm5719-llvm-cf67ffa50027baab4e8c838a73bddde215450807.zip
Rever 96389 and 96990. They are causing some miscompilation that I do not fully understand.
llvm-svn: 97782
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/X86/lsr-reuse-trunc.ll15
-rw-r--r--llvm/test/CodeGen/X86/sink-hoist.ll1
2 files changed, 4 insertions, 12 deletions
diff --git a/llvm/test/CodeGen/X86/lsr-reuse-trunc.ll b/llvm/test/CodeGen/X86/lsr-reuse-trunc.ll
index a663a220e62..d1d714491fa 100644
--- a/llvm/test/CodeGen/X86/lsr-reuse-trunc.ll
+++ b/llvm/test/CodeGen/X86/lsr-reuse-trunc.ll
@@ -1,19 +1,10 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -march=x86-64 | FileCheck %s
; Full strength reduction wouldn't reduce register pressure, so LSR should
; stick with indexing here.
-; Also checks andps and andnps shares the same constantpool. Previously llvm
-; will codegen two andps, one using 0x80000000, the other 0x7fffffff.
-; rdar://7323335
-
-; CHECK: movaps LCPI1_0
-; CHECK: movaps LCPI1_1
-; CHECK-NOT: movaps LCPI1_2
-; CHECK: movaps (%rsi,%rax,4), %xmm2
-; CHECK: andps
-; CHECK: andnps
-; CHECK: movaps %xmm2, (%rdi,%rax,4)
+; CHECK: movaps (%rsi,%rax,4), %xmm3
+; CHECK: movaps %xmm3, (%rdi,%rax,4)
; CHECK: addq $4, %rax
; CHECK: cmpl %eax, (%rdx)
; CHECK-NEXT: jg
diff --git a/llvm/test/CodeGen/X86/sink-hoist.ll b/llvm/test/CodeGen/X86/sink-hoist.ll
index e1d0fe76657..01d73736d6c 100644
--- a/llvm/test/CodeGen/X86/sink-hoist.ll
+++ b/llvm/test/CodeGen/X86/sink-hoist.ll
@@ -63,6 +63,7 @@ entry:
; CHECK: vv:
; CHECK: LCPI4_0(%rip), %xmm0
; CHECK: LCPI4_1(%rip), %xmm1
+; CHECK: LCPI4_2(%rip), %xmm2
; CHECK: align
; CHECK-NOT: LCPI
; CHECK: ret
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