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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-03-28 11:21:07 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-03-28 11:21:07 +0000 |
| commit | cdac172e2a6d8b1efc130ede138e157e21568c85 (patch) | |
| tree | f530e896fc53d92faa1f9c57a1848f67add41516 /llvm/test | |
| parent | 010924e35cedc390f7f2df31928ac9b19f754d6c (diff) | |
| download | bcm5719-llvm-cdac172e2a6d8b1efc130ede138e157e21568c85.tar.gz bcm5719-llvm-cdac172e2a6d8b1efc130ede138e157e21568c85.zip | |
Revert "[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader"
This reverts commit 0daf86291d3aa04d3cc280cd0ef24abdb0174981.
It was causing an assert in test/CodeGen/AMDGPU/amdpal.ll only on a
release-with-asserts build. I will resubmit the change when I have fixed
that.
Change-Id: If270594eba27a7dc4076bdeab3fa8e6bfda3288a
llvm-svn: 328695
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/amdpal.ll | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal.ll b/llvm/test/CodeGen/AMDGPU/amdpal.ll index 8d4c09cdeaf..c8f37fbe0b3 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal.ll @@ -52,36 +52,7 @@ entry: ret void } -; Check code sequence for amdpal use of scratch for alloca in a compute shader. -; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset -; 0 in a graphics shader. - -; PAL-LABEL: {{^}}scratch2_cs: -; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234 -; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0 -; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x10 -; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]: - -define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 { -entry: - %v = alloca [3 x i32], addrspace(5) - %v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0 - %v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1 - store i32 %extra, i32 addrspace(5)* %v0 - %v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)* - %vv = bitcast [2 x i32] addrspace(5)* %v1a to <2 x i32> addrspace(5)* - store <2 x i32> %in, <2 x i32> addrspace(5)* %vv - %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v1a, i32 0, i32 %idx - %x = load i32, i32 addrspace(5)* %e - %xf = bitcast i32 %x to float - call void @llvm.amdgcn.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0) - ret void -} - attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" } -declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) - - ; Check we have CS_NUM_USED_VGPRS in PAL metadata. ; PAL: .amd_amdgpu_pal_metadata {{.*}},0x10000027, |
