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authorTanya Lattner <tonic@nondot.org>2010-11-18 22:06:46 +0000
committerTanya Lattner <tonic@nondot.org>2010-11-18 22:06:46 +0000
commitcd680956505390d0b804dd806bb5e825b812a881 (patch)
tree35284a7cfde39f37fd86c6b84d94dd33f6afcf64 /llvm/test
parent2acd1621f44b9e01e5499b8b935eed108310bfbb (diff)
downloadbcm5719-llvm-cd680956505390d0b804dd806bb5e825b812a881.tar.gz
bcm5719-llvm-cd680956505390d0b804dd806bb5e825b812a881.zip
Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
Added test case. llvm-svn: 119749
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll b/llvm/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll
new file mode 100644
index 00000000000..b9cf3520235
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+define void @lshrIllegalType(<8 x i32>* %A) nounwind {
+ %tmp1 = load <8 x i32>* %A
+ %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
+ store <8 x i32> %tmp2, <8 x i32>* %A
+ ret void
+}
+
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