Optimize trivial branches in CodeGenPrepare, which often get created from the

lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127459

15 files changed, 17 insertions, 17 deletions

diff --git a/llvm/test/CodeGen/ARM/constants.ll b/llvm/test/CodeGen/ARM/constants.ll
index 542cf02f2a9..a66ee41fe19 100644
--- a/llvm/test/CodeGen/ARM/constants.ll
+++ b/llvm/test/CodeGen/ARM/constants.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm | FileCheck %s
+; RUN: llc < %s -march=arm -disable-cgp-branch-opts | FileCheck %s
 
 define i32 @f1() {
 ; CHECK: f1
diff --git a/llvm/test/CodeGen/CellSPU/jumptable.ll b/llvm/test/CodeGen/CellSPU/jumptable.ll
index 42b41b3bf29..87376ef6ed5 100644
--- a/llvm/test/CodeGen/CellSPU/jumptable.ll
+++ b/llvm/test/CodeGen/CellSPU/jumptable.ll
@@ -1,4 +1,4 @@
-;RUN: llc --march=cellspu %s -o - | FileCheck %s
+;RUN: llc --march=cellspu -disable-cgp-branch-opts %s -o - | FileCheck %s
 ; This is to check that emitting jumptables doesn't crash llc
 define i32 @test(i32 %param) {
 entry:
diff --git a/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll b/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
index 1f31dca0524..e698e00641f 100644
--- a/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
+++ b/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts | FileCheck %s
 
 	%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
 	%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
diff --git a/llvm/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/llvm/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
index 550b3efae99..ff68e665078 100644
--- a/llvm/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
+++ b/llvm/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
@@ -8,7 +8,7 @@ entry:
 ; CHECK: sub sp, #8
 ; CHECK: push
 ; CHECK: add r7, sp, #4
-; CHECK: subs r4, r7, #4
+; CHECK: sub.w r4, r7, #4
 ; CHECK: mov sp, r4
 ; CHECK-NOT: mov sp, r7
 ; CHECK: add sp, #8
diff --git a/llvm/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll b/llvm/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
index b2ed8fc7a67..ac3e80a7c11 100644
--- a/llvm/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
+++ b/llvm/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-cgp-branch-opts | FileCheck %s
 
 %struct.pix_pos = type { i32, i32, i32, i32, i32, i32 }
 
diff --git a/llvm/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll b/llvm/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
index 313728c1b56..d2140a10048 100644
--- a/llvm/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
+++ b/llvm/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
@@ -8,7 +8,7 @@ declare void @bar() nounwind optsize
 define void @foo() nounwind optsize {
 ; CHECK: foo:
 ; CHECK: push
-; CHECK: add r7, sp, #4
+; CHECK: mov r7, sp
 ; CHECK: sub sp, #4
 entry:
   %m.i = alloca %struct.buf*, align 4
diff --git a/llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
index b8c8cb122a1..edbf83405be 100644
--- a/llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
+++ b/llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
@@ -6,8 +6,6 @@ entry:
   br label %bb5
 
 bb5:                                              ; preds = %bb5, %entry
-; CHECK: %bb5
-; CHECK: bne
   br i1 undef, label %bb5, label %bb.nph
 
 bb.nph:                                           ; preds = %bb5
diff --git a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
index 6e8891bfd5b..bfe8ef53f56 100644
--- a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
+++ b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin | grep movw | not grep {, %e}
+; RUN: llc < %s -mtriple=i386-apple-darwin -disable-cgp-branch-opts | grep movw | not grep {, %e}
 
 	%struct.DBC_t = type { i32, i8*, i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i32*, i8, i16, %struct.DRVOPT*, i16 }
 	%struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* }
diff --git a/llvm/test/CodeGen/X86/MachineSink-PHIUse.ll b/llvm/test/CodeGen/X86/MachineSink-PHIUse.ll
index 728e3773601..3758fd8ce50 100644
--- a/llvm/test/CodeGen/X86/MachineSink-PHIUse.ll
+++ b/llvm/test/CodeGen/X86/MachineSink-PHIUse.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-appel-darwin -stats |& grep {machine-sink}
+; RUN: llc < %s -mtriple=x86_64-appel-darwin -disable-cgp-branch-opts -stats |& grep {machine-sink}
 
 define fastcc void @t() nounwind ssp {
 entry:
diff --git a/llvm/test/CodeGen/X86/personality.ll b/llvm/test/CodeGen/X86/personality.ll
index 6789bb0c0fb..705e489eb4c 100644
--- a/llvm/test/CodeGen/X86/personality.ll
+++ b/llvm/test/CodeGen/X86/personality.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s -check-prefix=X64
-; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X32
 ; PR1632
 
 define void @_Z1fv() {
diff --git a/llvm/test/CodeGen/X86/pr3366.ll b/llvm/test/CodeGen/X86/pr3366.ll
index f813e2e5880..1127b609321 100644
--- a/llvm/test/CodeGen/X86/pr3366.ll
+++ b/llvm/test/CodeGen/X86/pr3366.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep movzbl
+; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl
 ; PR3366
 
 define void @_ada_c34002a() nounwind {
diff --git a/llvm/test/CodeGen/X86/sext-i1.ll b/llvm/test/CodeGen/X86/sext-i1.ll
index 21c418d534e..574769b4308 100644
--- a/llvm/test/CodeGen/X86/sext-i1.ll
+++ b/llvm/test/CodeGen/X86/sext-i1.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86    | FileCheck %s -check-prefix=32
-; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=64
+; RUN: llc < %s -march=x86 -disable-cgp-branch-opts    | FileCheck %s -check-prefix=32
+; RUN: llc < %s -march=x86-64 -disable-cgp-branch-opts | FileCheck %s -check-prefix=64
 ; rdar://7573216
 ; PR6146
 
diff --git a/llvm/test/CodeGen/X86/zext-extract_subreg.ll b/llvm/test/CodeGen/X86/zext-extract_subreg.ll
index e61e8805a2f..4f1dde3c4f0 100644
--- a/llvm/test/CodeGen/X86/zext-extract_subreg.ll
+++ b/llvm/test/CodeGen/X86/zext-extract_subreg.ll
@@ -13,6 +13,7 @@ if.end:                                           ; preds = %if.end.i
 ; CHECK: %if.end
 ; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]]
 ; CHECK-NOT: movl [[REG]], [[REG]]
+; CHECK-NEXT: testl [[REG]], [[REG]]
 ; CHECK-NEXT: xorb
   %tmp138 = select i1 undef, i32 0, i32 %tmp7.i
   %tmp867 = zext i32 %tmp138 to i64
diff --git a/llvm/test/MC/ARM/simple-encoding.ll b/llvm/test/MC/ARM/simple-encoding.ll
index 0877e8e30c6..defeea947d5 100644
--- a/llvm/test/MC/ARM/simple-encoding.ll
+++ b/llvm/test/MC/ARM/simple-encoding.ll
@@ -1,4 +1,4 @@
-;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
+;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding -disable-cgp-branch-opts < %s | FileCheck %s
 
 
 ;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
diff --git a/llvm/test/Transforms/CodeGenPrepare/basic.ll b/llvm/test/Transforms/CodeGenPrepare/basic.ll
index 3b1fca328c5..ebf10f0e9df 100644
--- a/llvm/test/Transforms/CodeGenPrepare/basic.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/basic.ll
@@ -14,13 +14,14 @@ entry:
   br i1 %1, label %T, label %trap
 
 ; CHECK: entry:
-; HECK-NEXT: ret i32 4
+; CHECK-NEXT: br label %T
 
 trap:                                             ; preds = %0, %entry
   tail call void @llvm.trap() noreturn nounwind
   unreachable
 
 T:
+; CHECK: ret i32 4
   ret i32 4
 }