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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-10 15:05:09 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-10 15:05:09 +0000 |
| commit | ca57e53ded1f0c0d697c99c1d8442c2dce011d0c (patch) | |
| tree | f42742083ea44ed8863445bcb2f3c67509e08d41 /llvm/test | |
| parent | 40d33e75542f3a8a281cb180f2e72cbea0539ff8 (diff) | |
| download | bcm5719-llvm-ca57e53ded1f0c0d697c99c1d8442c2dce011d0c.tar.gz bcm5719-llvm-ca57e53ded1f0c0d697c99c1d8442c2dce011d0c.zip | |
[SelectionDAG] Add support for vector demandedelts in SRA opcodes
llvm-svn: 286461
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/known-bits-vector.ll | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/X86/known-bits-vector.ll b/llvm/test/CodeGen/X86/known-bits-vector.ll index 63ac9942dfa..0ba3cb106dc 100644 --- a/llvm/test/CodeGen/X86/known-bits-vector.ll +++ b/llvm/test/CodeGen/X86/known-bits-vector.ll @@ -156,18 +156,12 @@ define <4 x i32> @knownbits_mask_shl_shuffle_lshr(<4 x i32> %a0) nounwind { define <4 x i32> @knownbits_mask_ashr_shuffle_lshr(<4 x i32> %a0) nounwind { ; X32-LABEL: knownbits_mask_ashr_shuffle_lshr: ; X32: # BB#0: -; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 -; X32-NEXT: vpsrad $15, %xmm0, %xmm0 -; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] -; X32-NEXT: vpsrld $30, %xmm0, %xmm0 +; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: retl ; ; X64-LABEL: knownbits_mask_ashr_shuffle_lshr: ; X64: # BB#0: -; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 -; X64-NEXT: vpsrad $15, %xmm0, %xmm0 -; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] -; X64-NEXT: vpsrld $30, %xmm0, %xmm0 +; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-NEXT: retq %1 = and <4 x i32> %a0, <i32 131071, i32 -1, i32 -1, i32 131071> %2 = ashr <4 x i32> %1, <i32 15, i32 15, i32 15, i32 15> |
