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| author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-08-23 05:15:15 +0000 |
|---|---|---|
| committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-08-23 05:15:15 +0000 |
| commit | c4449df1b0ad3a02fe1a90bdeb564897236dc999 (patch) | |
| tree | a98cfd86dafd00033d970f6229f08eec9a3b2f06 /llvm/test | |
| parent | 0884b732202d043af4755d05aeb7fd3da8951a24 (diff) | |
| download | bcm5719-llvm-c4449df1b0ad3a02fe1a90bdeb564897236dc999.tar.gz bcm5719-llvm-c4449df1b0ad3a02fe1a90bdeb564897236dc999.zip | |
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate
On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris.
But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR).
This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate.
e.g. (x | 0xFFFFFFFF) should be
ori 3, 3, 65535
oris 3, 3, 65535
but LLVM generates without this patch
li 4, 0
oris 4, 4, 65535
ori 4, 4, 65535
or 3, 3, 4
Differential Revision: https://reviews.llvm.org/D34757
llvm-svn: 311526
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/ori_imm32.ll | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/ori_imm32.ll b/llvm/test/CodeGen/PowerPC/ori_imm32.ll new file mode 100644 index 00000000000..33d25f8e7de --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/ori_imm32.ll @@ -0,0 +1,96 @@ +; RUN: llc -verify-machineinstrs < %s -march=ppc64le | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s + +define i64 @ori_test_a(i64 %a) { +entry: +; CHECK-LABEL: @ori_test_a +; CHECK-DAG: ori 3, 3, 65535 +; CHECK-DAG: oris 3, 3, 65535 +; CHECK-NEXT: blr + %or = or i64 %a, 4294967295 + ret i64 %or +} + +define i64 @ori_test_b(i64 %a) { +entry: +; CHECK-LABEL: @ori_test_b +; CHECK: or 3, 3, {{[0-9]+}} +; CHECK-NEXT: blr + %or = or i64 %a, 4294967296 + ret i64 %or +} + +define i64 @ori_test_c(i64 %a) { +entry: +; CHECK-LABEL: @ori_test_c +; CHECK: ori 3, 3, 65535 +; CHECK-NEXT: blr + %or = or i64 %a, 65535 + ret i64 %or +} + +define i64 @ori_test_d(i64 %a) { +entry: +; CHECK-LABEL: @ori_test_d +; CHECK: oris 3, 3, 1 +; CHECK-NEXT: blr + %or = or i64 %a, 65536 + ret i64 %or +} + +define zeroext i32 @ori_test_e(i32 zeroext %a) { +entry: +; CHECK-LABEL: @ori_test_e +; CHECK-DAG: ori 3, 3, 65535 +; CHECK-DAG: oris 3, 3, 255 +; CHECK-NEXT: blr + %or = or i32 %a, 16777215 + ret i32 %or +} + +define i64 @xori_test_a(i64 %a) { +entry: +; CHECK-LABEL: @xori_test_a +; CHECK-DAG: xori 3, 3, 65535 +; CHECK-DAG: xoris 3, 3, 65535 +; CHECK-NEXT: blr + %xor = xor i64 %a, 4294967295 + ret i64 %xor +} + +define i64 @xori_test_b(i64 %a) { +entry: +; CHECK-LABEL: @xori_test_b +; CHECK: xor 3, 3, {{[0-9]+}} +; CHECK-NEXT: blr + %xor = xor i64 %a, 4294967296 + ret i64 %xor +} + +define i64 @xori_test_c(i64 %a) { +entry: +; CHECK-LABEL: @xori_test_c +; CHECK: xori 3, 3, 65535 +; CHECK-NEXT: blr + %xor = xor i64 %a, 65535 + ret i64 %xor +} + +define i64 @xori_test_d(i64 %a) { +entry: +; CHECK-LABEL: @xori_test_d +; CHECK: xoris 3, 3, 1 +; CHECK-NEXT: blr + %xor = xor i64 %a, 65536 + ret i64 %xor +} + +define zeroext i32 @xori_test_e(i32 zeroext %a) { +entry: +; CHECK-LABEL: @xori_test_e +; CHECK-DAG: xori 3, 3, 65535 +; CHECK-DAG: xoris 3, 3, 255 +; CHECK-NEXT: blr + %xor = xor i32 %a, 16777215 + ret i32 %xor +} |
