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| author | Geoff Berry <gberry@codeaurora.org> | 2016-04-12 15:50:19 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2016-04-12 15:50:19 +0000 |
| commit | c0739d83056ba36cd3941475bacc0f6d6dc6b2b8 (patch) | |
| tree | d3487f93ae4b0e7b210c1705c4256eb6aa359145 /llvm/test | |
| parent | c5cec39c0ee0f13cc9ab15a828b746e3cbb2fc03 (diff) | |
| download | bcm5719-llvm-c0739d83056ba36cd3941475bacc0f6d6dc6b2b8.tar.gz bcm5719-llvm-c0739d83056ba36cd3941475bacc0f6d6dc6b2b8.zip | |
[ScheduleDAGInstrs] Handle instructions with multiple MMOs
Summary:
In getUnderlyingObjectsForInstr(): Don't give up on instructions with
multiple MMOs, instead look through all the MMOs and if they all meet
the conservative criteria previously used for single MMO instructions,
then return all of the underlying objects derived from the MMOs.
The change to ScheduleDAGInstrs::buildSchedGraph() is needed to avoid
the case where multiple underlying objects are present and are related
in such a way that successive iterations of the loop end up adding a
dependency from an instruction to itself.
Reviewers: atrick, hfinkel
Subscribers: MatzeB, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D18093
llvm-svn: 266084
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-misched-multimmo.ll | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-multimmo.ll b/llvm/test/CodeGen/AArch64/arm64-misched-multimmo.ll new file mode 100644 index 00000000000..d4e8aa1a0a0 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-misched-multimmo.ll @@ -0,0 +1,23 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s + + +@G1 = common global [100 x i32] zeroinitializer, align 4 +@G2 = common global [100 x i32] zeroinitializer, align 4 + +; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling. +; +; CHECK-LABEL: # Machine code for function foo: Properties: <Post SSA +; CHECK: SU(2): %W{{[0-9]+}}<def>, %W{{[0-9]+}}<def> = LDPWi +; CHECK: Successors: +; CHECK-NOT: ch SU(4) +; CHECK: SU(3) +; CHECK: SU(4): STRWui %WZR, %X{{[0-9]+}} +define i32 @foo() { +entry: + %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4 + %1 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 1), align 4 + store i32 0, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G1, i64 0, i64 0), align 4 + %add = add nsw i32 %1, %0 + ret i32 %add +} |
