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| author | Kit Barton <kbarton@ca.ibm.com> | 2016-03-08 03:49:13 +0000 |
|---|---|---|
| committer | Kit Barton <kbarton@ca.ibm.com> | 2016-03-08 03:49:13 +0000 |
| commit | ba532dc81648aca4cdf9ba4f5f16ecbc971e811c (patch) | |
| tree | f9fec05711816d85f2bf85bf19d2679e770b129f /llvm/test | |
| parent | 4a795920e3e3fbef8c55956210b698f49d90f091 (diff) | |
| download | bcm5719-llvm-ba532dc81648aca4cdf9ba4f5f16ecbc971e811c.tar.gz bcm5719-llvm-ba532dc81648aca4cdf9ba4f5f16ecbc971e811c.zip | |
[Power9] Implement new vsx instructions: load, store instructions for vector and scalar
We follow the comments mentioned in http://reviews.llvm.org/D16842#344378 to
implement this new patch.
This patch implements the following vsx instructions:
Vector load/store:
lxv lxvx lxvb16x lxvl lxvll lxvh8x lxvwsx
stxv stxvb16x stxvh8x stxvl stxvll stxvx
Scalar load/store:
lxsd lxssp lxsibzx lxsihzx
stxsd stxssp stxsibx stxsihx
21 instructions
Phabricator: http://reviews.llvm.org/D16919
llvm-svn: 262906
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/Disassembler/PowerPC/vsx.txt | 75 | ||||
| -rw-r--r-- | llvm/test/MC/PowerPC/vsx.s | 101 |
2 files changed, 176 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/PowerPC/vsx.txt b/llvm/test/MC/Disassembler/PowerPC/vsx.txt index 5f153985044..ed7893db28d 100644 --- a/llvm/test/MC/Disassembler/PowerPC/vsx.txt +++ b/llvm/test/MC/Disassembler/PowerPC/vsx.txt @@ -625,3 +625,78 @@ # CHECK: xsrqpxp 1, 7, 27, 2 0xfc 0xe1 0xdc 0x4a + +# CHECK: lxv 61, 32752(31) +0xf7 0xbf 0x7f 0xf9 + +# CHECK: lxv 61, -32768(0) +0xf7 0xa0 0x80 0x09 + +# CHECK: stxv 61, 32752(31) +0xf7 0xbf 0x7f 0xfd + +# CHECK: stxv 61, -32768(0) +0xf7 0xa0 0x80 0x0d + +# CHECK: lxsd 31, -32768(0) +0xe7 0xe0 0x80 0x02 + +# CHECK: lxsd 31, 32764(12) +0xe7 0xec 0x7f 0xfe + +# CHECK: lxssp 31, -32768(0) +0xe7 0xe0 0x80 0x03 + +# CHECK: lxssp 31, 32764(12) +0xe7 0xec 0x7f 0xff + +# CHECK: stxsd 31, 32764(12) +0xf7 0xec 0x7f 0xfe + +# CHECK: stxssp 31, -32768(0) +0xf7 0xe0 0x80 0x03 + +# CHECK: lxvx 57, 12, 27 +0x7f 0x2c 0xda 0x19 + +# CHECK: lxsibzx 57, 12, 27 +0x7f 0x2c 0xde 0x1b + +# CHECK: lxsihzx 57, 12, 27 +0x7f 0x2c 0xde 0x5b + +# CHECK: lxvb16x 57, 12, 27 +0x7f 0x2c 0xde 0xd9 + +# CHECK: lxvh8x 57, 12, 27 +0x7f 0x2c 0xde 0x59 + +# CHECK: lxvl 57, 12, 27 +0x7f 0x2c 0xda 0x1b + +# CHECK: lxvll 57, 12, 27 +0x7f 0x2c 0xda 0x5b + +# CHECK: lxvwsx 57, 12, 27 +0x7f 0x2c 0xda 0xd9 + +# CHECK: stxsibx 57, 12, 27 +0x7f 0x2c 0xdf 0x1b + +# CHECK: stxsihx 57, 12, 27 +0x7f 0x2c 0xdf 0x5b + +# CHECK: stxvh8x 57, 12, 27 +0x7f 0x2c 0xdf 0x59 + +# CHECK: stxvb16x 57, 12, 27 +0x7f 0x2c 0xdf 0xd9 + +# CHECK: stxvx 57, 12, 27 +0x7f 0x2c 0xdb 0x19 + +# CHECK: stxvl 57, 12, 27 +0x7f 0x2c 0xdb 0x1b + +# CHECK: stxvll 57, 12, 27 +0x7f 0x2c 0xdb 0x5b diff --git a/llvm/test/MC/PowerPC/vsx.s b/llvm/test/MC/PowerPC/vsx.s index 172a0ea661b..ce341c35770 100644 --- a/llvm/test/MC/PowerPC/vsx.s +++ b/llvm/test/MC/PowerPC/vsx.s @@ -657,3 +657,104 @@ # CHECK-BE: xsrqpxp 1, 7, 27, 2 # encoding: [0xfc,0xe1,0xdc,0x4a] # CHECK-LE: xsrqpxp 1, 7, 27, 2 # encoding: [0x4a,0xdc,0xe1,0xfc] xsrqpxp 1, 7, 27, 2 + +# Load/Store Vector, test maximum and minimum displacement value +# CHECK-BE: lxv 61, 32752(31) # encoding: [0xf7,0xbf,0x7f,0xf9] +# CHECK-LE: lxv 61, 32752(31) # encoding: [0xf9,0x7f,0xbf,0xf7] + lxv 61, 32752(31) +# CHECK-BE: lxv 61, -32768(0) # encoding: [0xf7,0xa0,0x80,0x09] +# CHECK-LE: lxv 61, -32768(0) # encoding: [0x09,0x80,0xa0,0xf7] + lxv 61, -32768(0) +# CHECK-BE: stxv 61, 32752(31) # encoding: [0xf7,0xbf,0x7f,0xfd] +# CHECK-LE: stxv 61, 32752(31) # encoding: [0xfd,0x7f,0xbf,0xf7] + stxv 61, 32752(31) +# CHECK-BE: stxv 61, -32768(0) # encoding: [0xf7,0xa0,0x80,0x0d] +# CHECK-LE: stxv 61, -32768(0) # encoding: [0x0d,0x80,0xa0,0xf7] + stxv 61, -32768(0) + +# Load/Store DWord +# CHECK-BE: lxsd 31, -32768(0) # encoding: [0xe7,0xe0,0x80,0x02] +# CHECK-LE: lxsd 31, -32768(0) # encoding: [0x02,0x80,0xe0,0xe7] + lxsd 31, -32768(0) +# CHECK-BE: lxsd 31, 32764(12) # encoding: [0xe7,0xec,0x7f,0xfe] +# CHECK-LE: lxsd 31, 32764(12) # encoding: [0xfe,0x7f,0xec,0xe7] + lxsd 31, 32764(12) +# CHECK-BE: stxsd 31, 32764(12) # encoding: [0xf7,0xec,0x7f,0xfe] +# CHECK-LE: stxsd 31, 32764(12) # encoding: [0xfe,0x7f,0xec,0xf7] + stxsd 31, 32764(12) + +# Load SP from src, convert it to DP, and place in dword[0] +# CHECK-BE: lxssp 31, -32768(0) # encoding: [0xe7,0xe0,0x80,0x03] +# CHECK-LE: lxssp 31, -32768(0) # encoding: [0x03,0x80,0xe0,0xe7] + lxssp 31, -32768(0) +# CHECK-BE: lxssp 31, 32764(12) # encoding: [0xe7,0xec,0x7f,0xff] +# CHECK-LE: lxssp 31, 32764(12) # encoding: [0xff,0x7f,0xec,0xe7] + lxssp 31, 32764(12) + +# Convert DP of dword[0] to SP, and Store to dst +# CHECK-BE: stxssp 31, -32768(0) # encoding: [0xf7,0xe0,0x80,0x03] +# CHECK-LE: stxssp 31, -32768(0) # encoding: [0x03,0x80,0xe0,0xf7] + stxssp 31, -32768(0) + +# Load as Integer Byte/Halfword & Zero Indexed +# CHECK-BE: lxsibzx 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0x1b] +# CHECK-LE: lxsibzx 57, 12, 27 # encoding: [0x1b,0xde,0x2c,0x7f] + lxsibzx 57, 12, 27 +# CHECK-BE: lxsihzx 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0x5b] +# CHECK-LE: lxsihzx 57, 12, 27 # encoding: [0x5b,0xde,0x2c,0x7f] + lxsihzx 57, 12, 27 + +# Load Vector Halfword*8/Byte*16 Indexed +# CHECK-BE: lxvh8x 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0x59] +# CHECK-LE: lxvh8x 57, 12, 27 # encoding: [0x59,0xde,0x2c,0x7f] + lxvh8x 57, 12, 27 +# CHECK-BE: lxvb16x 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0xd9] +# CHECK-LE: lxvb16x 57, 12, 27 # encoding: [0xd9,0xde,0x2c,0x7f] + lxvb16x 57, 12, 27 + +# Load Vector Indexed +# CHECK-BE: lxvx 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0x19] +# CHECK-LE: lxvx 57, 12, 27 # encoding: [0x19,0xda,0x2c,0x7f] + lxvx 57, 12, 27 + +# Load Vector (Left-justified) with Length +# CHECK-BE: lxvl 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0x1b] +# CHECK-LE: lxvl 57, 12, 27 # encoding: [0x1b,0xda,0x2c,0x7f] + lxvl 57, 12, 27 +# CHECK-BE: lxvll 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0x5b] +# CHECK-LE: lxvll 57, 12, 27 # encoding: [0x5b,0xda,0x2c,0x7f] + lxvll 57, 12, 27 + +# Load Vector Word & Splat Indexed +# CHECK-BE: lxvwsx 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0xd9] +# CHECK-LE: lxvwsx 57, 12, 27 # encoding: [0xd9,0xda,0x2c,0x7f] + lxvwsx 57, 12, 27 + +# Store as Integer Byte/Halfword Indexed +# CHECK-BE: stxsibx 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0x1b] +# CHECK-LE: stxsibx 57, 12, 27 # encoding: [0x1b,0xdf,0x2c,0x7f] + stxsibx 57, 12, 27 +# CHECK-BE: stxsihx 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0x5b] +# CHECK-LE: stxsihx 57, 12, 27 # encoding: [0x5b,0xdf,0x2c,0x7f] + stxsihx 57, 12, 27 + +# Store Vector Halfword*8/Byte*16 Indexed +# CHECK-BE: stxvh8x 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0x59] +# CHECK-LE: stxvh8x 57, 12, 27 # encoding: [0x59,0xdf,0x2c,0x7f] + stxvh8x 57, 12, 27 +# CHECK-BE: stxvb16x 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0xd9] +# CHECK-LE: stxvb16x 57, 12, 27 # encoding: [0xd9,0xdf,0x2c,0x7f] + stxvb16x 57, 12, 27 + +# Store Vector Indexed +# CHECK-BE: stxvx 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x19] +# CHECK-LE: stxvx 57, 12, 27 # encoding: [0x19,0xdb,0x2c,0x7f] + stxvx 57, 12, 27 + +# Store Vector (Left-justified) with Length +# CHECK-BE: stxvl 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x1b] +# CHECK-LE: stxvl 57, 12, 27 # encoding: [0x1b,0xdb,0x2c,0x7f] + stxvl 57, 12, 27 +# CHECK-BE: stxvll 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x5b] +# CHECK-LE: stxvll 57, 12, 27 # encoding: [0x5b,0xdb,0x2c,0x7f] + stxvll 57, 12, 27 |

