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| author | Stefan Maksimovic <stefan.maksimovic@imgtec.com> | 2017-06-23 09:09:31 +0000 |
|---|---|---|
| committer | Stefan Maksimovic <stefan.maksimovic@imgtec.com> | 2017-06-23 09:09:31 +0000 |
| commit | b794c0a5ca23d5e225143e0ba9f8a3e6ca61d46e (patch) | |
| tree | 0c93afbd24a1fe61413a2a0ed9e3a9842a6e92fa /llvm/test | |
| parent | 575b25f2c0a5c38edd373262f0ab52d6afd3bfd9 (diff) | |
| download | bcm5719-llvm-b794c0a5ca23d5e225143e0ba9f8a3e6ca61d46e.tar.gz bcm5719-llvm-b794c0a5ca23d5e225143e0ba9f8a3e6ca61d46e.zip | |
[mips][msa] Splat.d endianness check
Before this change, it was always the first element of a vector that got splatted since the lower 6 bits of vshf.d $wd were always zero for little endian.
Additionally, masking has been performed for vshf via which splat.d is created.
Vshf has a property where if its first operand's elements have either bit 6 or 7 set, destination element is set to zero.
Initially masked with 63 to avoid this property, which would result in generation of and.v + vshf.d in all cases.
Masking with one results in generating a single splati.d instruction when possible.
Differential Revision: https://reviews.llvm.org/D32216
llvm-svn: 306090
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/3r_splat.ll | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/3r_splat.ll b/llvm/test/CodeGen/Mips/msa/3r_splat.ll index 78c485f4f86..a5f4999f852 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_splat.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_splat.ll @@ -92,3 +92,24 @@ declare <2 x i64> @llvm.mips.splat.d(<2 x i64>, i32) nounwind ; MIPS64-DAG: splat.d [[R4:\$w[0-9]+]], [[R3]][$4] ; MIPS64-DAG: st.d [[R4]], 0([[R2]]) ; MIPS32: .size llvm_mips_splat_d_test + +define void @llvm_mips_splat_d_arg_test(i32 %arg) { +entry: + %0 = tail call <2 x i64> @llvm.mips.splat.d(<2 x i64> <i64 12720328, i64 10580959>, i32 %arg) + store volatile <2 x i64> %0, <2 x i64>* @llvm_mips_splat_d_RES + ret void +} +; CHECK-LABEL: llvm_mips_splat_d_arg_test +; CHECK: ldi.w [[R1:\$w[0-9]+]], 1 +; CHECK: and.v [[R2:\$w[0-9]+]], {{\$w[0-9]+}}, [[R1]] +; CHECK: vshf.d [[R2]], {{.*}} + +define void @llvm_mips_splat_d_imm_test() { +entry: + %0 = tail call <2 x i64> @llvm.mips.splat.d(<2 x i64> <i64 12720328, i64 10580959>, i32 76) + store volatile<2 x i64> %0, <2 x i64>* @llvm_mips_splat_d_RES + ret void +} +; CHECK-LABEL: llvm_mips_splat_d_imm_test +; CHECK: splati. d {{.*}}, {{.*}}[0] +; CHECK-NOT: vshf.d |
