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| author | Nirav Dave <niravd@google.com> | 2017-08-01 13:45:35 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2017-08-01 13:45:35 +0000 |
| commit | b5cb48c6ae16d6ffc54c7d7281160bcc4acdc4cb (patch) | |
| tree | cdc1dd0b714825d56b5d329663d4f06dac24f68a /llvm/test | |
| parent | a2b4748bdc11ad679426be6b7fe67a3eff66063a (diff) | |
| download | bcm5719-llvm-b5cb48c6ae16d6ffc54c7d7281160bcc4acdc4cb.tar.gz bcm5719-llvm-b5cb48c6ae16d6ffc54c7d7281160bcc4acdc4cb.zip | |
[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.
Summary:
Allow SCALAR_TO_VECTOR of EXTRACT_VECTOR_ELT to reduce to
EXTRACT_SUBVECTOR of vector shuffle when output is smaller. Marginally
improves vector shuffle computations.
Reviewers: efriedma, RKSimon, spatel
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D35566
llvm-svn: 309680
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-neon-copy.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/neon-scalar-copy.ll | 11 |
2 files changed, 5 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll index 16834b7e315..2585676e1bd 100644 --- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll +++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll @@ -188,7 +188,7 @@ define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) { define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) { ; CHECK-LABEL: ins2f1: -; CHECK: mov {{d[0-9]+}}, {{v[0-9]+}}.d[1] +; CHECK: dup {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1] %tmp3 = extractelement <2 x double> %tmp1, i32 1 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0 ret <1 x double> %tmp4 diff --git a/llvm/test/CodeGen/AArch64/neon-scalar-copy.ll b/llvm/test/CodeGen/AArch64/neon-scalar-copy.ll index 3f770600ac5..2384e485fd7 100644 --- a/llvm/test/CodeGen/AArch64/neon-scalar-copy.ll +++ b/llvm/test/CodeGen/AArch64/neon-scalar-copy.ll @@ -79,8 +79,7 @@ define half @test_dup_hv8H_0(<8 x half> %v) #0 { define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 { ; CHECK-LABEL: test_vector_dup_bv16B: - ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.b[14] - ; CHECK-NEXT: fmov s0, [[W]] + ; CHECK-NEXT: dup v0.16b, v0.b[14] ; CHECK-NEXT: ret %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14> ret <1 x i8> %shuffle.i @@ -96,8 +95,7 @@ define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 { define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 { ; CHECK-LABEL: test_vector_dup_hv8H: - ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.h[7] - ; CHECK-NEXT: fmov s0, [[W]] + ; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: ret %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7> ret <1 x i16> %shuffle.i @@ -113,8 +111,7 @@ define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 { define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 { ; CHECK-LABEL: test_vector_dup_sv4S: - ; CHECK-NEXT: mov [[W:w[0-9]+]], v0.s[3] - ; CHECK-NEXT: fmov s0, [[W]] + ; CHECK-NEXT: dup v0.4s, v0.s[3] ; CHECK-NEXT: ret %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3> ret <1 x i32> %shuffle @@ -138,7 +135,7 @@ define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 { define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 { ; CHECK-LABEL: test_vector_copy_dup_dv2D: - ; CHECK-NEXT: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1] + ; CHECK-NEXT: dup v0.2d, v1.d[1] ; CHECK-NEXT: ret %vget_lane = extractelement <2 x i64> %c, i32 1 %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0 |
