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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-07-03 15:55:54 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-07-03 15:55:54 +0000 |
| commit | b5c68a6717082eed1afe80c01e3cf2283ea90f7f (patch) | |
| tree | bf2d2270cbeb7dfe54dff0a1cc7852f0d341d837 /llvm/test | |
| parent | 52db9a4fe6757c8c76d1ef205ce4368b3444bf0b (diff) | |
| download | bcm5719-llvm-b5c68a6717082eed1afe80c01e3cf2283ea90f7f.tar.gz bcm5719-llvm-b5c68a6717082eed1afe80c01e3cf2283ea90f7f.zip | |
[X86][SSE4A] Test SSE4A shuffle combining on SSE42 capable target as well
llvm-svn: 307038
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-combining-sse4a.ll | 53 |
1 files changed, 36 insertions, 17 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-sse4a.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-sse4a.ll index 899c3eb5ed2..92cfbe124e7 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-sse4a.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-sse4a.ll @@ -1,9 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE4A +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2,+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE42 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,+sse4a| FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2,+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 ; -; Combine tests involving SSE41 target shuffles (BLEND,INSERTPS,MOVZX) +; Combine tests involving SSE4A target shuffles (EXTRQI,INSERTQI) declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) @@ -25,11 +26,17 @@ define <16 x i8> @combine_extrqi_pshufb_16i8(<16 x i8> %a0) { } define <8 x i16> @combine_extrqi_pshufb_8i16(<8 x i16> %a0) { -; SSE-LABEL: combine_extrqi_pshufb_8i16: -; SSE: # BB#0: -; SSE-NEXT: extrq {{.*#+}} xmm0 = xmm0[2,3,4,5],zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] -; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] -; SSE-NEXT: retq +; SSSE3-LABEL: combine_extrqi_pshufb_8i16: +; SSSE3: # BB#0: +; SSSE3-NEXT: extrq {{.*#+}} xmm0 = xmm0[2,3,4,5],zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] +; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] +; SSSE3-NEXT: retq +; +; SSE42-LABEL: combine_extrqi_pshufb_8i16: +; SSE42: # BB#0: +; SSE42-NEXT: extrq {{.*#+}} xmm0 = xmm0[2,3,4,5],zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] +; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; SSE42-NEXT: retq ; ; AVX-LABEL: combine_extrqi_pshufb_8i16: ; AVX: # BB#0: @@ -44,11 +51,17 @@ define <8 x i16> @combine_extrqi_pshufb_8i16(<8 x i16> %a0) { } define <16 x i8> @combine_insertqi_pshufb_16i8(<16 x i8> %a0, <16 x i8> %a1) { -; SSE-LABEL: combine_insertqi_pshufb_16i8: -; SSE: # BB#0: -; SSE-NEXT: insertq {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u] -; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] -; SSE-NEXT: retq +; SSSE3-LABEL: combine_insertqi_pshufb_16i8: +; SSSE3: # BB#0: +; SSSE3-NEXT: insertq {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u] +; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] +; SSSE3-NEXT: retq +; +; SSE42-LABEL: combine_insertqi_pshufb_16i8: +; SSE42: # BB#0: +; SSE42-NEXT: insertq {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u] +; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; SSE42-NEXT: retq ; ; AVX-LABEL: combine_insertqi_pshufb_16i8: ; AVX: # BB#0: @@ -61,11 +74,17 @@ define <16 x i8> @combine_insertqi_pshufb_16i8(<16 x i8> %a0, <16 x i8> %a1) { } define <8 x i16> @combine_insertqi_pshufb_8i16(<8 x i16> %a0, <8 x i16> %a1) { -; SSE-LABEL: combine_insertqi_pshufb_8i16: -; SSE: # BB#0: -; SSE-NEXT: insertq {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7,u,u,u,u,u,u,u,u] -; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] -; SSE-NEXT: retq +; SSSE3-LABEL: combine_insertqi_pshufb_8i16: +; SSSE3: # BB#0: +; SSSE3-NEXT: insertq {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7,u,u,u,u,u,u,u,u] +; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] +; SSSE3-NEXT: retq +; +; SSE42-LABEL: combine_insertqi_pshufb_8i16: +; SSE42: # BB#0: +; SSE42-NEXT: insertq {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7,u,u,u,u,u,u,u,u] +; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; SSE42-NEXT: retq ; ; AVX-LABEL: combine_insertqi_pshufb_8i16: ; AVX: # BB#0: |

