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| author | Hal Finkel <hfinkel@anl.gov> | 2016-09-02 00:28:20 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2016-09-02 00:28:20 +0000 |
| commit | b54579fab6571501f9e82a3e413ad36fd34aaa75 (patch) | |
| tree | 90547e1d913da5243389b2bd243efcfea2bc786c /llvm/test | |
| parent | 1e8218cc095cb7c7a4897e846b60e0672ed49271 (diff) | |
| download | bcm5719-llvm-b54579fab6571501f9e82a3e413ad36fd34aaa75.tar.gz bcm5719-llvm-b54579fab6571501f9e82a3e413ad36fd34aaa75.zip | |
[PowerPC] Don't apply the PPC64 address-formation peephole for offsets greater than 7
When applying our address-formation PPC64 peephole, we are reusing the @ha TOC
addis value with the low parts associated with different offsets (i.e.
different effective symbol addends). We were assuming this was okay so long as
the offsets were less than the alignment of the global variable being accessed.
This ignored the fact, however, that the TOC base pointer itself need only be
8-byte aligned. As a result, what we were doing is legal only for offsets less
than 8 regardless of the alignment of the object being accessed.
Fixes PR28727.
llvm-svn: 280441
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/peephole-align.ll | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/PowerPC/peephole-align.ll b/llvm/test/CodeGen/PowerPC/peephole-align.ll index cb0dde91242..1be84170734 100644 --- a/llvm/test/CodeGen/PowerPC/peephole-align.ll +++ b/llvm/test/CodeGen/PowerPC/peephole-align.ll @@ -208,12 +208,13 @@ entry: ; CHECK-LABEL: test_d2: ; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, d2v@toc@ha +; CHECK: addi [[BASEV:[0-9]+]], [[REGSTRUCT]], d2v@toc@l ; CHECK-DAG: ld [[REG0_0:[0-9]+]], d2v@toc@l([[REGSTRUCT]]) -; CHECK-DAG: ld [[REG1_0:[0-9]+]], d2v@toc@l+8([[REGSTRUCT]]) +; CHECK-DAG: ld [[REG1_0:[0-9]+]], 8([[BASEV]]) ; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 ; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 ; CHECK-DAG: std [[REG0_1]], d2v@toc@l([[REGSTRUCT]]) -; CHECK-DAG: std [[REG1_1]], d2v@toc@l+8([[REGSTRUCT]]) +; CHECK-DAG: std [[REG1_1]], 8([[BASEV]]) define void @test_d2() nounwind { entry: @@ -229,7 +230,8 @@ entry: ; register 3 is the return value, so it should be chosen ; CHECK-LABEL: test_singleuse: ; CHECK: addis 3, 2, d2v@toc@ha -; CHECK: ld 3, d2v@toc@l+8(3) +; CHECK: addi 3, 3, d2v@toc@l +; CHECK: ld 3, 8(3) define i64 @test_singleuse() nounwind { entry: %0 = load i64, i64* getelementptr inbounds (%struct.d2, %struct.d2* @d2v, i32 0, i32 1), align 8 |
