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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-31 21:52:27 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-31 21:52:27 +0000 |
| commit | b50eb8dc2b3cb0005eb0187e1cb9fe7a68a0a070 (patch) | |
| tree | 1f875e2ae1e0edf29eb006cba4f3bd5919445df1 /llvm/test | |
| parent | 1d2151781b7ab164c56f2d9694725e6373df5eb4 (diff) | |
| download | bcm5719-llvm-b50eb8dc2b3cb0005eb0187e1cb9fe7a68a0a070.tar.gz bcm5719-llvm-b50eb8dc2b3cb0005eb0187e1cb9fe7a68a0a070.zip | |
AMDGPU: Fix introducing stack access on unaligned v16i8
llvm-svn: 280298
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll | 49 |
2 files changed, 53 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll b/llvm/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll index 08bdc3aba55..adba6bbb51d 100644 --- a/llvm/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll +++ b/llvm/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll @@ -1,15 +1,13 @@ -; XFAIL: * -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s -; XUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s ; ; EG-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount: -; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] +; EG: MEM_{{.*}} MSKOR [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG-NOT: BFE ; EG: ADD_INT ; EG: LSHL -; EG: ASHR [[RES]] +; EG: ASHR ; EG: LSHL -; EG: ASHR [[RES]] +; EG: ASHR ; EG: LSHR {{\*?}} [[ADDR]] ; Works with the align 2 removed diff --git a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll index 129748afd93..453c981db1a 100644 --- a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll +++ b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll @@ -552,4 +552,53 @@ define void @constant_align4_merge_load_2_i32(i32 addrspace(2)* %p, i32 addrspac ret void } +; SI-LABEL: {{^}}local_load_align1_v16i8: +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 + +; SI: ScratchSize: 0{{$}} +define void @local_load_align1_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> addrspace(3)* %in) #0 { + %ld = load <16 x i8>, <16 x i8> addrspace(3)* %in, align 1 + store <16 x i8> %ld, <16 x i8> addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}local_store_align1_v16i8: +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 + +; SI: ScratchSize: 0{{$}} +define void @local_store_align1_v16i8(<16 x i8> addrspace(3)* %out) #0 { + store <16 x i8> zeroinitializer, <16 x i8> addrspace(3)* %out, align 1 + ret void +} + attributes #0 = { nounwind } |
