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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-21 19:27:36 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-21 19:27:36 +0000 |
| commit | b2e6811ec17c8220670d8c3b7c23a3b85878e18c (patch) | |
| tree | a2e2c9e9d12d662818888fa7803529e817dfa89a /llvm/test | |
| parent | c2a44e4c3c4cdcb5a68789ad53ca61c853150c79 (diff) | |
| download | bcm5719-llvm-b2e6811ec17c8220670d8c3b7c23a3b85878e18c.tar.gz bcm5719-llvm-b2e6811ec17c8220670d8c3b7c23a3b85878e18c.zip | |
AMDGPU: Remove dead declarations from MIR tests
llvm-svn: 295755
Diffstat (limited to 'llvm/test')
3 files changed, 5 insertions, 48 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir index 47f0e168a72..84d3baa4c9a 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -mcpu=SI -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | @@ -14,21 +14,7 @@ ret void } - declare { i1, i64 } @llvm.SI.if(i1) - - declare { i1, i64 } @llvm.SI.else(i64) - - declare i64 @llvm.SI.break(i64) - - declare i64 @llvm.SI.if.break(i1, i64) - - declare i64 @llvm.SI.else.break(i64, i64) - - declare i1 @llvm.SI.loop(i64) - - declare void @llvm.SI.end.cf(i64) - - attributes #0 = { "target-cpu"="SI" } + attributes #0 = { nounwind } ... --- diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir index d73503223aa..fec7a5d7a38 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -mcpu=SI -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | @@ -14,21 +14,7 @@ ret void } - declare { i1, i64 } @llvm.SI.if(i1) - - declare { i1, i64 } @llvm.SI.else(i64) - - declare i64 @llvm.SI.break(i64) - - declare i64 @llvm.SI.if.break(i1, i64) - - declare i64 @llvm.SI.else.break(i64, i64) - - declare i1 @llvm.SI.loop(i64) - - declare void @llvm.SI.end.cf(i64) - - attributes #0 = { "target-cpu"="SI" } + attributes #0 = { nounwind } ... --- diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir index a4e77f281ea..10c8128b3ce 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir @@ -22,22 +22,7 @@ store float %1, float addrspace(1)* %out ret void } - - declare { i1, i64 } @llvm.SI.if(i1) - - declare { i1, i64 } @llvm.SI.else(i64) - - declare i64 @llvm.SI.break(i64) - - declare i64 @llvm.SI.if.break(i1, i64) - - declare i64 @llvm.SI.else.break(i64, i64) - - declare i1 @llvm.SI.loop(i64) - - declare void @llvm.SI.end.cf(i64) - - attributes #0 = { "target-cpu"="SI" } + attributes #0 = { nounwind } ... --- |
