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authorCraig Topper <craig.topper@intel.com>2018-07-12 21:58:03 +0000
committerCraig Topper <craig.topper@intel.com>2018-07-12 21:58:03 +0000
commitb0053b79d62f520d732573e5c50031b8dbf55a91 (patch)
tree2ee52fbc4884eafe9ef759397dc08c32d8e8dca5 /llvm/test
parente7cdb7edf74ab80fb24dc72468051e38a907ede1 (diff)
downloadbcm5719-llvm-b0053b79d62f520d732573e5c50031b8dbf55a91.tar.gz
bcm5719-llvm-b0053b79d62f520d732573e5c50031b8dbf55a91.zip
Revert r336950 and r336951 "[X86] Add AVX512 equivalents of some isel patterns so we get EVEX instructions." and "foo"
One of them had a bad title and they should have been squashed. llvm-svn: 336953
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll13
-rw-r--r--llvm/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll13
-rw-r--r--llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll13
-rw-r--r--llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll17
4 files changed, 18 insertions, 38 deletions
diff --git a/llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
index 009ea22400e..fce52bf6699 100644
--- a/llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
@@ -2558,15 +2558,10 @@ define <4 x float> @test_mm_sqrt_ss(<4 x float> %a0) {
; SSE-NEXT: sqrtss %xmm0, %xmm0 # encoding: [0xf3,0x0f,0x51,0xc0]
; SSE-NEXT: ret{{[l|q]}} # encoding: [0xc3]
;
-; AVX1-LABEL: test_mm_sqrt_ss:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xfa,0x51,0xc0]
-; AVX1-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-;
-; AVX512-LABEL: test_mm_sqrt_ss:
-; AVX512: # %bb.0:
-; AVX512-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x51,0xc0]
-; AVX512-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+; AVX-LABEL: test_mm_sqrt_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xfa,0x51,0xc0]
+; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%ext = extractelement <4 x float> %a0, i32 0
%sqrt = call float @llvm.sqrt.f32(float %ext)
%ins = insertelement <4 x float> %a0, float %sqrt, i32 0
diff --git a/llvm/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll b/llvm/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll
index cd593676f31..d153d2f42d6 100644
--- a/llvm/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll
+++ b/llvm/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll
@@ -34,15 +34,10 @@ define <4 x float> @test_x86_sse_sqrt_ss(<4 x float> %a0) {
; SSE-NEXT: sqrtss %xmm0, %xmm0 ## encoding: [0xf3,0x0f,0x51,0xc0]
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
-; AVX1-LABEL: test_x86_sse_sqrt_ss:
-; AVX1: ## %bb.0:
-; AVX1-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x51,0xc0]
-; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512-LABEL: test_x86_sse_sqrt_ss:
-; AVX512: ## %bb.0:
-; AVX512-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x51,0xc0]
-; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; AVX-LABEL: test_x86_sse_sqrt_ss:
+; AVX: ## %bb.0:
+; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x51,0xc0]
+; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
ret <4 x float> %res
}
diff --git a/llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
index e9af4ebca72..be389890bb7 100644
--- a/llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
@@ -4896,15 +4896,10 @@ define <2 x double> @test_mm_sqrt_sd(<2 x double> %a0, <2 x double> %a1) nounwin
; SSE-NEXT: movapd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x28,0xc1]
; SSE-NEXT: ret{{[l|q]}} # encoding: [0xc3]
;
-; AVX1-LABEL: test_mm_sqrt_sd:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vsqrtsd %xmm0, %xmm1, %xmm0 # encoding: [0xc5,0xf3,0x51,0xc0]
-; AVX1-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-;
-; AVX512-LABEL: test_mm_sqrt_sd:
-; AVX512: # %bb.0:
-; AVX512-NEXT: vsqrtsd %xmm0, %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf3,0x51,0xc0]
-; AVX512-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+; AVX-LABEL: test_mm_sqrt_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: vsqrtsd %xmm0, %xmm1, %xmm0 # encoding: [0xc5,0xf3,0x51,0xc0]
+; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%ext = extractelement <2 x double> %a0, i32 0
%sqrt = call double @llvm.sqrt.f64(double %ext)
%ins = insertelement <2 x double> %a1, double %sqrt, i32 0
diff --git a/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll b/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
index 1c1900deafe..54529b177e5 100644
--- a/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
+++ b/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
@@ -34,15 +34,10 @@ define <2 x double> @test_x86_sse2_sqrt_sd(<2 x double> %a0) {
; SSE-NEXT: sqrtsd %xmm0, %xmm0 ## encoding: [0xf2,0x0f,0x51,0xc0]
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
-; AVX1-LABEL: test_x86_sse2_sqrt_sd:
-; AVX1: ## %bb.0:
-; AVX1-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0]
-; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512-LABEL: test_x86_sse2_sqrt_sd:
-; AVX512: ## %bb.0:
-; AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x51,0xc0]
-; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; AVX-LABEL: test_x86_sse2_sqrt_sd:
+; AVX: ## %bb.0:
+; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0]
+; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0) ; <<2 x double>> [#uses=1]
ret <2 x double> %res
}
@@ -68,7 +63,7 @@ define <2 x double> @test_x86_sse2_sqrt_sd_vec_load(<2 x double>* %a0) {
; X86-AVX512: ## %bb.0:
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX512-NEXT: vmovapd (%eax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0x00]
-; X86-AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x51,0xc0]
+; X86-AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0]
; X86-AVX512-NEXT: retl ## encoding: [0xc3]
;
; X64-SSE-LABEL: test_x86_sse2_sqrt_sd_vec_load:
@@ -86,7 +81,7 @@ define <2 x double> @test_x86_sse2_sqrt_sd_vec_load(<2 x double>* %a0) {
; X64-AVX512-LABEL: test_x86_sse2_sqrt_sd_vec_load:
; X64-AVX512: ## %bb.0:
; X64-AVX512-NEXT: vmovapd (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0x07]
-; X64-AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x51,0xc0]
+; X64-AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0]
; X64-AVX512-NEXT: retq ## encoding: [0xc3]
%a1 = load <2 x double>, <2 x double>* %a0, align 16
%res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a1) ; <<2 x double>> [#uses=1]
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