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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-06-28 09:54:28 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-06-28 09:54:28 +0000
commitabebe4c746e34220fdd1da6783dd3920125260d0 (patch)
treefe63b1ad2c5dbbce5e8f8683bacd5c3c2a68b0cb /llvm/test
parent388af14f859b58a98c2400e4b4469922ea788d2f (diff)
downloadbcm5719-llvm-abebe4c746e34220fdd1da6783dd3920125260d0.tar.gz
bcm5719-llvm-abebe4c746e34220fdd1da6783dd3920125260d0.zip
[DAGCombiner] Ensure we use the correct CC result type in visitSDIV
We could get away with it for constant folded cases, but not for rL335719. Thanks to Krzysztof Parzyszek for noticing. llvm-svn: 335821
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/Hexagon/sdiv-minsigned.ll14
-rw-r--r--llvm/test/CodeGen/X86/combine-sdiv.ll25
2 files changed, 33 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/Hexagon/sdiv-minsigned.ll b/llvm/test/CodeGen/Hexagon/sdiv-minsigned.ll
new file mode 100644
index 00000000000..06b4dc1ceda
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/sdiv-minsigned.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; REQUIRES: asserts
+
+; This checks for a bug in the DAG combiner where a SETCC was created with
+; an illegal return type. Make sure it compiles successfully.
+; CHECK: r0 = cmp.eq(r0,##-2147483648)
+
+define i32 @f0(i32 %a0) #0 {
+entry:
+ %v0 = sdiv i32 %a0, -2147483648
+ ret i32 %v0
+}
+
+attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" }
diff --git a/llvm/test/CodeGen/X86/combine-sdiv.ll b/llvm/test/CodeGen/X86/combine-sdiv.ll
index f9939ddfeff..5d2547b3b47 100644
--- a/llvm/test/CodeGen/X86/combine-sdiv.ll
+++ b/llvm/test/CodeGen/X86/combine-sdiv.ll
@@ -77,12 +77,25 @@ define <4 x i32> @combine_vec_sdiv_by_minsigned(<4 x i32> %x) {
; AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; AVX1-NEXT: retq
;
-; AVX2ORLATER-LABEL: combine_vec_sdiv_by_minsigned:
-; AVX2ORLATER: # %bb.0:
-; AVX2ORLATER-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; AVX2ORLATER-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; AVX2ORLATER-NEXT: vpsrld $31, %xmm0, %xmm0
-; AVX2ORLATER-NEXT: retq
+; AVX2-LABEL: combine_vec_sdiv_by_minsigned:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
+; AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: combine_vec_sdiv_by_minsigned:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
+; AVX512F-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
+; AVX512F-NEXT: vpsrld $31, %xmm0, %xmm0
+; AVX512F-NEXT: retq
+;
+; AVX512BW-LABEL: combine_vec_sdiv_by_minsigned:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vpcmpeqd {{.*}}(%rip){1to4}, %xmm0, %k1
+; AVX512BW-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z}
+; AVX512BW-NEXT: retq
;
; XOP-LABEL: combine_vec_sdiv_by_minsigned:
; XOP: # %bb.0:
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