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authorTim Northover <Tim.Northover@arm.com>2013-02-06 09:13:13 +0000
committerTim Northover <Tim.Northover@arm.com>2013-02-06 09:13:13 +0000
commita80c4c1a080b4f34a78e06996e0f41179329d2b5 (patch)
tree92fcfbedeefbc9ac0c2a6c220c3be146efd1986e /llvm/test
parent91a51c5a7c2299cdcf0a292a94f3a89e516425bc (diff)
downloadbcm5719-llvm-a80c4c1a080b4f34a78e06996e0f41179329d2b5.tar.gz
bcm5719-llvm-a80c4c1a080b4f34a78e06996e0f41179329d2b5.zip
Add AArch64 CRC32 instructions
These instructions are a late addition to the architecture, and may yet end up behind an optional attribute, but for now they're available at all times. llvm-svn: 174496
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/MC/AArch64/basic-a64-instructions.s17
-rw-r--r--llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt17
2 files changed, 34 insertions, 0 deletions
diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s
index e3b1ea8326a..ad3064e5e52 100644
--- a/llvm/test/MC/AArch64/basic-a64-instructions.s
+++ b/llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -1435,6 +1435,23 @@ _func:
// Data-processing (2 source)
//------------------------------------------------------------------------------
+ crc32b w5, w7, w20
+ crc32h w28, wzr, w30
+ crc32w w0, w1, w2
+ crc32x w7, w9, x20
+ crc32cb w9, w5, w4
+ crc32ch w13, w17, w25
+ crc32cw wzr, w3, w5
+ crc32cx w18, w16, xzr
+// CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a]
+// CHECK: crc32h w28, wzr, w30 // encoding: [0xfc,0x47,0xde,0x1a]
+// CHECK: crc32w w0, w1, w2 // encoding: [0x20,0x48,0xc2,0x1a]
+// CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a]
+// CHECK: crc32cb w9, w5, w4 // encoding: [0xa9,0x50,0xc4,0x1a]
+// CHECK: crc32ch w13, w17, w25 // encoding: [0x2d,0x56,0xd9,0x1a]
+// CHECK: crc32cw wzr, w3, w5 // encoding: [0x7f,0x58,0xc5,0x1a]
+// CHECK: crc32cx w18, w16, xzr // encoding: [0x12,0x5e,0xdf,0x9a]
+
udiv w0, w7, w10
udiv x9, x22, x4
sdiv w12, w21, w0
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 2de5f700c11..4fa2d5078b2 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -1020,6 +1020,23 @@
# Data-processing (2 source)
#------------------------------------------------------------------------------
+# CHECK: crc32b w5, w7, w20
+# CHECK: crc32h w28, wzr, w30
+# CHECK: crc32w w0, w1, w2
+# CHECK: crc32x w7, w9, x20
+# CHECK: crc32cb w9, w5, w4
+# CHECK: crc32ch w13, w17, w25
+# CHECK: crc32cw wzr, w3, w5
+# CHECK: crc32cx w18, w16, xzr
+0xe5 0x40 0xd4 0x1a
+0xfc 0x47 0xde 0x1a
+0x20 0x48 0xc2 0x1a
+0x27 0x4d 0xd4 0x9a
+0xa9 0x50 0xc4 0x1a
+0x2d 0x56 0xd9 0x1a
+0x7f 0x58 0xc5 0x1a
+0x12 0x5e 0xdf 0x9a
+
# CHECK: udiv w0, w7, w10
# CHECK: udiv x9, x22, x4
# CHECK: sdiv w12, w21, w0
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